The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 23, 2018

Filed:

Dec. 24, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Robert L. Bristol, Portland, OR (US);

Manish Chandhok, Beaverton, OR (US);

Jasmeet S. Chawla, Hillsboro, OR (US);

Florian Gstrein, Portland, OR (US);

Eungnak Han, Portland, OR (US);

Rami Hourani, Portland, OR (US);

Kevin Lin, Beaverton, OR (US);

Richard E. Schenker, Portland, OR (US);

Todd R. Younkin, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 23/528 (2013.01); H01L 21/76816 (2013.01); H01L 21/76832 (2013.01); H01L 21/76849 (2013.01); H01L 21/76897 (2013.01); H01L 23/53238 (2013.01); H01L 23/53252 (2013.01); H01L 23/53266 (2013.01); H01L 23/53295 (2013.01);
Abstract

Embodiments of the invention include an interconnect structure and methods of forming such structures. In an embodiment, the interconnect structure may include an interlayer dielectric (ILD) with a first hardmask layer over a top surface of the ILD. Certain embodiments include one or more first interconnect lines in the ILD and a first dielectric cap positioned above each of the first interconnect lines. For example a surface of the first dielectric cap may contact a top surface of the first hardmask layer. Embodiments may also include one or more second interconnect lines in the ILD arranged in an alternating pattern with the first inter-connect lines. In an embodiment, a second dielectric cap is formed over a top surface of each of the second interconnect lines. For example, a surface of the second dielectric cap contacts a top surface of the first hardmask layer.


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