The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 28, 2020
Filed:
Mar. 30, 2016
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Manish Chandhok, Beaverton, OR (US);
Richard E. Schenker, Portland, OR (US);
Hui Jae Yoo, Hillsboro, OR (US);
Kevin L. Lin, Beaverton, OR (US);
Jasmeet S. Chawla, Hillsboro, OR (US);
Stephanie A. Bojarski, Beaverton, OR (US);
Satyarth Suri, Portland, OR (US);
Colin T. Carver, Portland, OR (US);
Sudipto Naskar, Portland, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 21/768 (2006.01); H01L 21/311 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76802 (2013.01); H01L 21/31144 (2013.01); H01L 21/76847 (2013.01); H01L 21/76883 (2013.01); H01L 23/5226 (2013.01);
Abstract
A plurality of interconnect features are formed in an interconnect layer on a first insulating layer on a substrate. An opening in the first insulating layer is formed through at least one of the interconnect features. A gap fill layer is deposited in the opening.