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For the Inventor, By the Inventor

Hsinchu, Taiwan

Hun-Jan Tao

This inventor holds 137 USPTO granted patents and 1 published patent application, primarily in Semiconductor Technology (CPC class H01L2-1302). Top assignees: Taiwan Semiconductor Manufacturing Comp. Ltd., Grand Plastic Technology Corporation Taiwan, Other. Active years: 1997-2015.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Hun-Jan Tao. Retrieved from https://idiyas.com/inventor/hun-jan-tao

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 137 

% Patents Active = 56.2

Average Co-Inventor Count = 3.4

ph-index = 21

Forward Citations = 2,547(Granted Patents)

Forward Citations (Not Self Cited) = 2,516(Dec 10, 2025)


Inventors with similar research interests:

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Location History:

  • Hsinchu Hsien, TW (2004)
  • Hsin-chu, TW (1997 - 2015)

Company Filing History:

goldMedal135 out of 42,872 
 
Taiwan Semiconductor Manufacturing Comp. Ltd.
 patents
silverMedal1 out of 1 
 
Grand Plastic Technology Corporation Taiwan
 patent
bronzeMedal1 out of 834,513 
Other
 patents

Years Active: 1997-2015

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Areas of Expertise:
Gate Structure
Dielectric Materials
Interconnects
CMOS Devices
Multi-Metal-Oxide
Low K Dielectric
Trench Structures
FET Devices
Dual Damascene
Backside Contacts
Process Methods
Photoresist Treatment
137 patents (USPTO):Explore Patents
1. 9218974 - Sidewall free CESL for enlarging ILD gap-fill window (2015-12-22),
2. 8999834 - Sidewall-free CESL for enlarging ILD gap-fill window (2015-04-07),
3. 8970015 - Method for protecting a gate structure during contact formation (2015-03-03),
4. 8658525 - Methods for a gate replacement process (2014-02-25),
5. 8648446 - Method for protecting a gate structure during contact formation (2014-02-11),
6. 8529783 - Method for backside polymer reduction in dry-etch process (2013-09-10),
7. 8497169 - Method for protecting a gate structure during contact formation (2013-07-30),
8. 8415799 - Dual damascene interconnect in hybrid dielectric (2013-04-09),
9. 8384159 - Semiconductor devices and methods with bilayer dielectrics (2013-02-26),
10. 8372755 - Multilayer hard mask (2013-02-12),
11. 8367563 - Methods for a gate replacement process (2013-02-05),
12. 8299508 - CMOS structure with multiple spacers (2012-10-30),
13. 8283222 - Method to form a semiconductor device having gate dielectric layers of varying thickness (2012-10-09),
14. 8202776 - Method for protecting a gate structure during contact formation (2012-06-19),
15. 8148270 - Low K dielectric surface damage control (2012-04-03),

Title: The Inventive Journey of Hun-Jan Tao: Paving the Way with Patents

Introduction:

In the world of innovations and patents, Hun-Jan Tao has emerged as a prolific inventor, contributing significantly to the field of integrated circuit structures. Hailing from Hsinchu, Taiwan, Tao has an impressive portfolio of 137 patents, with his latest inventions focused on enhancing the ILD (Interlayer Dielectric) gap-fill window. This article delves into his career highlights and collaborations, shedding light on his notable contributions to the field.

Latest Patents:

Among his impressive array of patents, two recent innovations stand out: "Sidewall free CESL for enlarging ILD gap-fill window" and "Sidewall-free CESL for enlarging ILD gap-fill window." Both integrated circuit structures involve a first gate strip, a gate spacer, and a contact etch stop layer (CESL). Notably, these inventions introduce a unique aspect where a portion of the sidewall of the gate spacer is devoid of CESL, enabling a larger gap-fill window for the ILD.

Career Highlights:

Throughout his career, Tao has worked with renowned companies at the forefront of the semiconductor industry. Notably, he has made significant contributions during his tenure at Taiwan Semiconductor Manufacturing Company Limited (TSMC), a global leader in semiconductor manufacturing. At TSMC, Tao applied his innovative ideas and expertise, resulting in numerous patents that have advanced the efficiency and performance of integrated circuits.

Collaborations:

Innovation thrives on collaboration, and Hun-Jan Tao has had the opportunity to work alongside some notable individuals in the field. One of his important collaborations was with Chia-Shiung Tsai, a fellow inventor renowned for his work in integrated circuits and semiconductor technologies. Another noteworthy association was with Yuan-Hung Chiu, who has made significant contributions to the development of advanced semiconductor processing techniques. These collaborations reflect Tao's dedication to pushing the boundaries of innovation through teamwork.

Conclusion:

Hun-Jan Tao's journey as an inventor has been truly remarkable. With a vast number of patents to his name, his contributions have undoubtedly influenced the field of integrated circuit structures. Through his latest patents focusing on enlarging ILD gap-fill windows, he has demonstrated a keen understanding of industry challenges and a commitment to finding novel solutions. As Tao continues to expand his inventive prowess, we can expect further advancements in integrated circuit technologies, inspiring new possibilities for the industry as a whole.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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