Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

Grand Plastic Technology Corporation Taiwan

Hun-Jan Tao

Chia-Shiung Tsai

Yuan-Hung Chiu

Peng-Fu Hsu

Chao-Cheng Chen

Huan-Just Lin

Baw-Ching Perng

Ming-Huan Tsai

Bor-Wen Chan

Jyu-Horng Shieh

Fang-Cheng Chen

Yi-Nien Su

Ju-Wang Hsu

Li-Te S Lin

Shiang-Bau Wang

Ming-Jie Huang

Hsien-Kuang Chiu

Jin Ying

Da-Yuan Lee

Chun-Li Chou

Yi-Chen Huang

Fong-Yu Yen

Kong-Beng Thei

Chia Shiung Tsai

Pei-Chao Su

Hong-Dyi Chang

Mong-Song Liang

Yu-Lien Huang

Ming-Ching Chang

Ryan Chia-Jen Chen

Kuang-Yuan Hsu

Harry Hak-Lay Chuang

Matt Yeh

Bor Chiuan Hsieh

Yong-Tian Hou

Jang-Shiang Tsai

Kuei-Ying Lee

Shau-Lin Shue

Syun-Ming Jang Jang

Carlos H Diaz

Wei-Yang Lee

Chih-Hsin Ko

Fu-Liang Yang

Jeng-Horng Chen

Ling-Yen Yeh

Cheng-Lung Hung

Liang-Gi Yao

Xiong-Fei Yu

Yi-Ming Sheu

Chen-Nan Yeh

Chu-Yun Fu

Peng-Soon Lim

Chi-Chun Chen

Yuan-Chang Huang

Yi-Shien Mor

Huang-Ming Chen

Vencent Chang

Chih-Cheng Wang

Hui OuYang

Han-Pin Chung

Yi-Chun Huang

Ming-Hong Hsieh

Yao-Yi Cheng

Cheng-Ku Chen

Ming Huan Tsai

Hui Ouyang

Chen-Hua Douglas Yu

Chih-Hao Wang

Jen-Cheng Liu

Wen-Chih Chiou

Harry-Hak-Lay Chuang

Shih-Chang Chen

Anthony Yen

Yung-Cheng Lu

Chung-Chi Ko

Chii-Ming M Wu

Weng Chang

Tsang-Jiuh Wu

Chia-Jen Chen

Chang-Yun Chang

Chun-Chieh Lin

Hung-Chang Hsieh

Yih-Ann Lin

Chung-Long Chang

Hao-Ming Lien

Vincent Chang

Bing-Yue Tsui

Jenn-Ming Huang

Mong Song Liang

Chun-Hon Chen

Yen-Shih Ho

Ming-Hsin Huang

Hui-Chang Yu

Sheng-Da Liu

Ying-Ying Wang

Chao-Tzung Tsai

Ming-Huei Lui

Lawrence Chiang Sheu

Li-Shiun Chen

Zhong Tang Xuan

An integrated circuit structure includes a first gate strip; a gate spacer on a sidewall of the first gate strip; and a contact etch stop layer (CESL) having a bottom portion lower than a top surface of the gate spacer, wherein a portion of a sidewall of the gate spacer has no CESL formed thereon.

Sidewall free CESL for enlarging ILD gap-fill window

Sidewall-free CESL for enlarging ILD gap-fill window

Various semiconductor devices are disclosed. An exemplary device includes: a substrate; a gate structure disposed over the substrate, wherein the gate structure includes a source region and a drain region; a first etch stop layer disposed over the gate structure, a second etch stop layer disposed over the source region and the drain region; a dielectric layer disposed over the substrate; and a gate contact, a source contact, and a drain contact. The dielectric layer is disposed over both etch stop layers. The gate contact extends through the dielectric layer and the first etch stop layer to the gate structure. The source contact and the drain contact extend through the dielectric layer and the second etch stop layer respectively to the source region and the drain region.

Method for protecting a gate structure during contact formation

A method for fabricating a semiconductor device is disclosed. In one embodiment, the method may include providing a substrate; forming a gate structure including a first dummy gate over the substrate; removing the first dummy gate from the gate structure to form a trench; forming an interfacial layer, high-k dielectric layer, and capping layer to partially fill in the trench; forming a second dummy gate over the capping layer, wherein the second dummy gate fills the trench; and replacing the second dummy gate with a metal gate. In one embodiment, the method may include providing a substrate; forming an interfacial layer over the substrate; forming a high-k dielectric layer over the interfacial layer; forming an etch stop layer over the high-k dielectric layer; forming a capping layer including a low thermal budget silicon over the etch stop layer; forming a dummy gate layer over the capping layer; forming a gate structure; and performing a gate replacement process.

Methods for a gate replacement process

A method for preventing the formation of contaminating polymeric films on the backsides of semiconductor substrates includes providing an oxygen-impregnated focus ring and/or an oxygen-impregnated chuck that releases oxygen during etching operations. The method further provides delivering oxygen gas to the substrate by mixing oxygen in the cooling gas mixture, maintaining the focus ring at a temperature no greater than the substrate temperature during etching and cleaning the substrate using a two step plasma cleaning sequence that includes suspending the substrate above the chuck.

Method for backside polymer reduction in dry-etch process

Various methods for protecting a gate structure during contact formation are disclosed. An exemplary method includes: forming a gate structure over a substrate, wherein the gate structure includes a gate and the gate structure interposes a source region and a drain region disposed in the substrate; patterning a first etch stop layer such that the first etch stop layer is disposed on the source region and the drain region; patterning a second etch stop layer such that the second etch stop layer is disposed on the gate structure; and forming a source contact, a drain contact, and a gate contact, wherein the source contact and the drain contact extend through the first etch stop layer and the gate contact extends through the second etch stop layer, wherein the forming the source contact, the drain contact, and the gate contact includes simultaneously removing the first etch stop layer and the second etch stop layer to expose the gate, source region, and drain region.

A semiconductor device. A diffusion barrier layer overlies a substrate. An adhesion promoting layer overlies the diffusion barrier layer. A first dielectric layer between the diffusion barrier layer and the adhesion promoting layer comprises at least one via opening through the diffusion barrier layer and the adhesion promoting layer. A second dielectric layer overlies the adhesion promoting layer, comprising a trench opening above the via opening. A metal interconnect fills the via and trench openings.

Dual damascene interconnect in hybrid dielectric

A semiconductor device is disclosed that includes: a substrate; a first dielectric layer formed over the substrate and formed of a first high-k material, the first high-k material selected from the group consisting of HfO, HfSiO, HfSiON, HfTaO, HfTiO, HfTiTaO, HfAlON, and HfZrO; a second dielectric layer formed over the first dielectric layer and formed of a second high-k material, the second high-k material being different than the first high-k material and selected from the group consisting of HfO, HfSiO, HfSiON, HfTaO, HfTiO, HfTiTaO, HfAlON, and HfZrO; and a metal gate formed over the second dielectric layer. The first dielectric layer includes ions selected from the group consisting of N, O, and Si.

Semiconductor devices and methods with bilayer dielectrics

A method for fabricating a semiconductor device is disclosed. In an embodiment, the method may include providing a semiconductor substrate; forming gate material layers over the semiconductor substrate; forming a multi-layer hard mask layer over the gate material layers, wherein the multi-layer hard mask layer includes a plurality of film stacks, each film stack having a silicon oxide layer and a carbon-containing material layer, each film stack having a thickness equal to or less than about 10 angstrom; patterning the multi-layer hard mask layer, forming an opening of the multi-hard mask layer; etching the gate material layers within the opening of the multi-layer hard mask layer, forming a gate structure; performing a tilt-angle ion implantation process to the semiconductor substrate, wherein a first remaining thickness of the multi-layer hard mask layer is less than a first thickness; and thereafter performing an epitaxy growth to the semiconductor substrate, wherein a second remaining thickness of the multi-layer hard mask layer is greater than a second thickness.

Multilayer hard mask

A semiconductor device includes a substrate having shallow trench isolation and source/drain regions located therein, a gate stack located on the substrate between the source/drain regions, a first gate spacer on the sidewall of the gate stack, and a second gate spacer on the sidewall of the first gate spacer.

CMOS structure with multiple spacers

A method for fabricating an integrated circuit device is disclosed which includes providing a substrate having first, second, and third regions; and forming first, second, and third gate structures in the first, second, and third regions, respectively. The first, second, and third gate structures include a gate dielectric layer, the gate dielectric layer being a first thickness in the first gate structure, a second thickness in the second gate structure, and a third thickness in the third gate structure. Forming the gate dielectric layer of the first, second, and third thicknesses can include forming an etching barrier layer over the gate dielectric layer in at least one of the first, second, or third regions while forming the first, second, and third gate structures, and/or prior to forming the gate dielectric layer in at least one of the first, second, or third regions, performing an implantation process on the at least one region.

Method to form a semiconductor device having gate dielectric layers of varying thickness

A method for fabricating a semiconductor device is disclosed. The method includes providing a substrate; forming at least one gate structure over the substrate; forming a plurality of doped regions in the substrate; forming an etch stop layer over the substrate; removing a first portion of the etch stop layer, wherein a second portion of the etch stop layer remains over the plurality of doped regions; forming a hard mask layer over the substrate; removing a first portion of the hard mask layer, wherein a second portion of the hard mask layer remains over the at least one gate structure; and forming a first contact through the second portion of the hard mask layer to the at least one gate structure, and a second contact through the second portion of the etch stop layer to the plurality of doped regions.

A method of removing a silicon nitride or a nitride-based bottom etch stop layer in a copper damascene structure by etching the bottom etch stop layer is disclosed, with the method using a high density, high radical concentration plasma containing fluorine and oxygen to minimize back sputtering of copper underlying the bottom etch stop layer and surface roughening of the low-k interlayer dielectric caused by the plasma.

Low K dielectric surface damage control

Growing community of inventors

Hsinchu, Taiwan

Hun-Jan Tao