The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 07, 2015
Filed:
Feb. 20, 2014
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Inventors:
Han-Pin Chung, Fongshan, TW;
Bor Chiuan Hsieh, Taoyuan County, TW;
Shiang-Bau Wang, Pingzchen, TW;
Hun-Jan Tao, Hsin-Chu, TW;
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/3205 (2006.01); H01L 21/28 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 23/485 (2006.01); H01L 29/66 (2006.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28017 (2013.01); H01L 21/76829 (2013.01); H01L 21/76837 (2013.01); H01L 21/823425 (2013.01); H01L 21/823475 (2013.01); H01L 23/485 (2013.01); H01L 29/66545 (2013.01); H01L 27/088 (2013.01); H01L 29/665 (2013.01); H01L 29/6659 (2013.01); H01L 2924/0002 (2013.01); Y10S 438/97 (2013.01);
Abstract
An integrated circuit structure includes a first gate strip; a gate spacer on a sidewall of the first gate strip; and a contact etch stop layer (CESL) having a bottom portion lower than a top surface of the gate spacer, wherein a portion of a sidewall of the gate spacer has no CESL formed thereon.