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For the Inventor, By the Inventor

Taipei, Taiwan

Huan-Sheng Wei

This inventor holds 14 USPTO granted patents and 3 published patent applications, primarily in Semiconductor Devices. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2018-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Huan-Sheng Wei. Retrieved from https://idiyas.com/inventor/huan-sheng-wei

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 14 

% Patents Active = 100.0

Average Co-Inventor Count = 5.4

ph-index = 3

Forward Citations = 142(Granted Patents)


Location History:

  • Taipei, TW (2018 - 2024)
  • Hsinchu, TW (2022 - 2024)

Company Filing History:

goldMedal14 out of 42,965 
 
Taiwan Semiconductor Manufacturing Comp. Ltd.
 patents

Years Active: 2018-2026

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Areas of Expertise:
Memory Circuit
Ferroelectric Memory
Multi-Gate Device
Semiconductor Structure
Threshold Voltage Adjustment
Carrier Structures
Fabrication Methods
Semiconductor Wire
14 patents (USPTO):Explore Patents
1. 12670943 - Memory circuit and write method (2026-06-30),
2. 12543322 - Ferroelectric memory device with carrier structures (2026-02-03),
3. 11955554 - Method of fabricating a multi-gate device (2024-04-09),
4. 11942134 - Memory circuit and write method (2024-03-26),
5. 11508427 - Memory circuit and write method (2022-11-22),
6. 11393926 - Multi-gate device (2022-07-19),
7. 11158542 - Semiconductor device structure with semiconductor wire (2021-10-26),
8. 11145762 - Multi-gate device (2021-10-12),
9. 11043423 - Threshold voltage adjustment for a gate-all-around semiconductor structure (2021-06-22),
10. 10879130 - Semiconductor device structure with semiconductor wire (2020-12-29),
11. 10438851 - Threshold voltage adjustment for a gate-all-around semiconductor structure (2019-10-08),
12. 10290548 - Semiconductor device structure with semiconductor wire (2019-05-14),
13. 10290546 - Threshold voltage adjustment for a gate-all-around semiconductor structure (2019-05-14),
14. 10008603 - Multi-gate device and method of fabrication thereof (2018-06-26),

Title: Huan-Sheng Wei: Innovator in Semiconductor Technology

Introduction

Huan-Sheng Wei is a prominent inventor based in Taipei, Taiwan, known for his significant contributions to semiconductor technology. With a total of 12 patents to his name, Wei has made remarkable advancements in the field, particularly in the fabrication of multi-gate devices and memory circuits.

Latest Patents

Wei's latest patents include a method of fabricating a multi-gate device. This method involves providing a fin with multiple types of epitaxial layers, where the second type of epitaxial layers is oxidized in the source/drain region. A portion of the first layer of the second type is removed in the channel region to create an opening for a gate structure. Another notable patent is for a memory circuit that features a memory array with multiple memory cells. Each cell includes an n-type channel layer made of metal oxide material, and the circuit is designed to apply varying gate voltages during write operations.

Career Highlights

Huan-Sheng Wei is currently employed at Taiwan Semiconductor Manufacturing Company Limited, a leading firm in the semiconductor industry. His work has been instrumental in developing innovative technologies that enhance the performance and efficiency of semiconductor devices.

Collaborations

Wei has collaborated with notable colleagues such as Hung-Li Chiang and Chung-Cheng Wu, contributing to various projects that push the boundaries of semiconductor technology.

Conclusion

Huan-Sheng Wei's contributions to the field of semiconductor technology through his patents and collaborations highlight his role as a key innovator. His work continues to influence advancements in the industry, making him a significant figure in the realm of inventions.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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