The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 22, 2021

Filed:

Oct. 07, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Hung-Li Chiang, Taipei, TW;

Szu-Wei Huang, Hsinchu, TW;

Huan-Sheng Wei, Taipei, TW;

Jon-Hsu Ho, New Taipei, TW;

Chih Chieh Yeh, Taipei, TW;

Wen-Hsing Hsieh, Hsinchu, TW;

Chung-Cheng Wu, Hsin-Chu County, TW;

Yee-Chia Yeo, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 29/49 (2006.01); H01L 29/786 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823412 (2013.01); H01L 21/02236 (2013.01); H01L 21/02532 (2013.01); H01L 21/02603 (2013.01); H01L 21/28123 (2013.01); H01L 21/30604 (2013.01); H01L 21/823456 (2013.01); H01L 27/088 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/4966 (2013.01); H01L 29/66545 (2013.01); H01L 29/78618 (2013.01); H01L 29/78651 (2013.01); H01L 29/78696 (2013.01);
Abstract

A semiconductor structure includes a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers. The first and second semiconductor layers have different material compositions. A dummy gate stack is formed over an uppermost first semiconductor layer. A first etching process is performed to remove portions of the second semiconductor layer that are not disposed below the dummy gate stack, thereby forming a plurality of voids. The first etching process has an etching selectivity between the first semiconductor layer and the second semiconductor layer. Thereafter, a second etching process is performed to enlarge the voids.


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