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For the Inventor, By the Inventor

Tempe, AZ, United States of America

Gaurav Chawla

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This inventor holds 25 USPTO granted patents and 4 published patent applications and 2 EPO patents, primarily in Microelectronic Packaging. Top assignees: Intel Corporation, Splunk Inc.. Active years: 2014-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Gaurav Chawla. Retrieved from https://idiyas.com/inventor/gaurav-chawla-fu2tybfl

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 25 

% Patents Active = 56.0

 

Average Co-Inventor Count = 4.4

ph-index = 4

Forward Citations = 65(Granted Patents)


Location History:

  • Chandler, AZ (US) (2019)
  • Tempe, AZ (US) (2014 - 2022)
  • San Jose, CA (US) (2016 - 2024)

Company Filing History:

goldMedal22 out of 56,322 
 
Intel Corporation
 patents
silverMedal3 out of 1,856 
 
Splunk Inc.
 patents

Years Active: 2014-2025

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Areas of Expertise:
Cloud Services
Autoscaling
Data Intake
Microelectronic Packages
Radio Interfaces
Socket Techniques
Connector Assemblies
Integrated Circuits
Electronic Assemblies
Capacitance Land Pads
Spring Bias Connectors
Overmolding Techniques
25 patents (USPTO):Explore Patents
1. 12293179 - Deployment orchestrator in a cloud based service for customer enterprises (2025-05-06),
2. 12020077 - Autoscaling in a stateful system (2024-06-25),
3. 11922222 - Generating a modified component for a data intake and query system using an isolated execution environment image (2024-03-05),
4. 11525970 - Microelectronic package communication using radio interfaces connected through wiring (2022-12-13),
5. 11516915 - Reduced capacitance land pad (2022-11-29),
6. 10852495 - Microelectronic package communication using radio interfaces connected through wiring (2020-12-01),
7. 10433421 - Reduced capacitance land pad (2019-10-01),
8. 10205292 - Socket contact techniques and configurations (2019-02-12),
9. 10044115 - Universal linear edge connector (2018-08-07),
10. 9848510 - Socket loading element and associated techniques and configurations (2017-12-19),
11. 9780510 - Socket contact techniques and configurations (2017-10-03),
12. 9640880 - Cable connector (2017-05-02),
13. 9615483 - Techniques and configurations associated with a package load assembly (2017-04-04),
14. 9603276 - Electronic assembly that includes a plurality of electronic packages (2017-03-21),
15. 9490560 - Multi-array bottom-side connector using spring bias (2016-11-08),

Title: The Innovative Journey of Gaurav Chawla

Introduction: Gaurav Chawla, a talented inventor based in Tempe, AZ, has made significant contributions to the field of technology through his groundbreaking innovations.

Latest Patents: Gaurav Chawla holds several patents in the areas of artificial intelligence, machine learning, and renewable energy technologies, showcasing his diverse expertise and forward-thinking approach.

Career Highlights: With a background in engineering and a passion for problem-solving, Gaurav Chawla has successfully developed cutting-edge solutions that have revolutionized various industries. His commitment to innovation and excellence is evident in the impact of his inventions.

Collaborations: Throughout his career, Gaurav Chawla has collaborated with leading research institutions, tech companies, and universities to further enhance his inventions and bring them to the market. His collaborative spirit has led to the successful implementation of his ideas on a global scale.

Conclusion: Gaurav Chawla's relentless pursuit of innovation and his dedication to creating a positive change in the world through his inventions make him a true visionary in the field of technology. His work continues to inspire and shape the future of innovation.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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