The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 29, 2022

Filed:

Sep. 03, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Zhichao Zhang, Chandler, AZ (US);

Tao Wu, Chandler, AZ (US);

Gaurav Chawla, Tempe, AZ (US);

Jeffrey Lee, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/11 (2006.01); H05K 3/40 (2006.01); H05K 3/46 (2006.01); H05K 3/34 (2006.01); H05K 1/02 (2006.01);
U.S. Cl.
CPC ...
H05K 1/113 (2013.01); H05K 3/34 (2013.01); H05K 3/40 (2013.01); H05K 3/46 (2013.01); H05K 3/4661 (2013.01); H05K 1/025 (2013.01); H05K 1/0243 (2013.01); H05K 3/3452 (2013.01); H05K 2201/0969 (2013.01); H05K 2201/09663 (2013.01); H05K 2201/09881 (2013.01); H05K 2201/10719 (2013.01); Y10T 29/49165 (2015.01);
Abstract

A land grid array (LGA) land pad having reduced capacitance is disclosed. The conductive portion of a land pad that overlaps a parallel ground plane within the substrate is reduced by one or more non-conductive voids though the thickness of the conductive portion of the land pad. The voids may allow the contact area of the land pad, as defined by the perimeter of the land pad, to remain the same while reducing the conductive portion that overlaps the parallel ground plane. Capacitance between the land pad and the parallel ground plane is reduced by an amount proportional to the reduction in overlapping conductive area.


Find Patent Forward Citations

Loading…