Chun-Hsien Yu

This inventor holds 20 USPTO granted patents and 4 published patent applications, primarily in Semiconductor Packaging. Top assignees: Phoenix Pioneer Technology Co., Ltd., Advanced Semiconductor Engineering, Inc.. Active years: 2017-2024.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chun-Hsien Yu. Retrieved from https://idiyas.com/inventor/chun-hsien-yu

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 20 (Patent Applications = 4)

% Patents Active = 90.0

Average Co-Inventor Count = 2.7

ph-index = 1

Forward Citations = 8(Granted Patents)

Company Filing History:

20 out of 76

Phoenix Pioneer Technology Co., Ltd.

patents

1 out of 1,964

Advanced Semiconductor Engineering, Inc.

patents

where one patent can have more than one assignee

Years Active: 2017-2024

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Areas of Expertise:

Flip-Chip Substrate

Fabrication Method

Electronic Package

Heat Dissipating Metal Sheet

Shielding Layers

Package Structure

Core Substrate

Carrier Board

Inductance Traces

Build-Up Layers

Substrate Structure

Packaging Module

20 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 12154866 - Method of fabricating a flip-chip package core substrate with build-up layers (2024-11-26),

2. 12094922 - Inductance traces protected through shielding layers (2024-09-17),

3. 11791281 - Package substrate and method for manufacturing the same (2023-10-17),

4. 11749612 - Semiconductor package device (2023-09-05),

5. 11646331 - Package substrate (2023-05-09),

6. 11508673 - Semiconductor packaging substrate, fabrication method and packaging process thereof (2022-11-22),

7. 11476204 - Flip-chip packaging substrate and method for fabricating the same (2022-10-18),

8. 11450597 - Semiconductor package substrate having heat dissipating metal sheet on solder pads, method for fabricating the same, and electronic package having the same (2022-09-20),

9. 11404348 - Semiconductor package carrier board, method for fabricating the same, and electronic package having the same (2022-08-02),

10. 11335630 - Semiconductor package substrate, electronic package and methods for fabricating the same (2022-05-17),

11. 11183447 - Flip-chip package substrate and method for fabricating the same (2021-11-23),

12. 11139230 - Flip-chip package substrate and method for preparing the same (2021-10-05),

13. 10745818 - Method of fabricating package substrates (2020-08-18),

14. 10366906 - Electronic package and its package substrate (2019-07-30),

15. 10347575 - Package substrate and its fabrication method (2019-07-09),

Title: The Innovative Mind of Chun-Hsien Yu

Introduction: Chun-Hsien Yu, a talented inventor hailing from Hsinchu County, Taiwan, is known for his groundbreaking contributions to the field of technology and innovation.

Latest Patents: Chun-Hsien Yu holds several patents in the areas of semiconductor technology, renewable energy, and advanced materials. His most recent patents focus on enhancing the efficiency of solar cells and developing cutting-edge semiconductor devices.

Career Highlights: With a career spanning over two decades, Chun-Hsien Yu has worked with leading technology companies and research institutions to push the boundaries of innovation. He has been instrumental in developing new technologies that have revolutionized the semiconductor industry.

Collaborations: Chun-Hsien Yu has collaborated with top researchers, engineers, and scientists from around the world to bring his innovative ideas to life. His collaborative efforts have led to the successful development of several groundbreaking technologies that have had a significant impact on various industries.

Conclusion: Chun-Hsien Yu's passion for innovation and his relentless pursuit of technological advancement have solidified his reputation as a visionary inventor. His contributions to the field of technology continue to inspire future generations of inventors and innovators.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

4 patents pending: