The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 05, 2023

Filed:

Nov. 29, 2021
Applicant:

Phoenix Pioneer Technology Co., Ltd., Hsinchu County, TW;

Inventors:

Chun-Hsien Yu, Hsinchu County, TW;

Shih-Ping Hsu, Hsinchu County, TW;

Hsien-Ming Tsai, Hsinchu County, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 23/538 (2006.01); H01L 23/31 (2006.01); H01L 25/10 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5387 (2013.01); H01L 23/3121 (2013.01); H01L 23/5383 (2013.01); H01L 25/105 (2013.01); H01L 24/16 (2013.01); H01L 24/48 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/48235 (2013.01);
Abstract

A semiconductor package device includes a flexible carrier, a first chip, a second chip, a first molding layer, a first adhesive layer and a second molding layer. The flexible carrier has a flexible layer and a rigid layer. The flexible layer has a patterned build-up circuit. The rigid layer is connected to a portion surface of the flexible layer. The position that the flexible layer connected to the rigid layer is formed a first carrying part and a second carrying part. The region of the flexible layer between the first carrying part and the second carrying part without the rigid layer is formed as a first flexible part. The first chip is connected to the first carrying part by flip-chip manner and the second chip is connected to the second carrying part by flip-chip manner. The first molding layer covers the first chip and the second molding layer covers the second chip. The first adhesive layer is connected between the first molding layer and the second carrying part.


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