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For the Inventor, By the Inventor

Clifton Park, NY, United States of America

Charan V V S Surisetty

This inventor holds 38 USPTO granted patents and 2 published patent applications, primarily in Semiconductor Technology. Top assignees: International Business Machines Corporation, Elpis Technologies Inc., Globalfoundries Inc.. Active years: 2016-2021.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Charan V V S Surisetty. Retrieved from https://idiyas.com/inventor/charan-v-v-s-surisetty

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 38 

% Patents Active = 39.5

Average Co-Inventor Count = 4.0

ph-index = 6

Forward Citations = 129(Granted Patents)


Location History:

  • Cliffton Park, NY (US) (2017)
  • Clifton Park, NY (US) (2016 - 2021)

Company Filing History:

goldMedal31 out of 166,409 
 
International Business Machines Corporation
 patents
silverMedal4 out of 52 
 
Elpis Technologies Inc.
 patents
bronzeMedal3 out of 5,671 
 
Globalfoundries Inc.
 patents
4. 2 out of 1,909 
 
Adeia Semiconductor Bonding Technologies Inc.
 patents
where one patent can have more than one assignee

Years Active: 2016-2021

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Areas of Expertise:
Contact Resistance
FinFETs
MOL Capacitance
Epitaxial Structures
Low-K Gate Cap
High Voltage Transistor
Local Interconnect
Trench Isolation
Strained FinFET
Inter-Level Dielectric
Self-Aligned Contact
Epitaxial Stressor
38 patents (USPTO):Explore Patents
1. 11038055 - Method and structure of improving contact resistance for passive and long channel devices (2021-06-15),
2. 10937861 - Semiconductor structures including middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack (2021-03-02),
3. 10811410 - Simultaneously fabricating a high voltage transistor and a FinFET (2020-10-20),
4. 10790284 - Spacer for trench epitaxial structures (2020-09-29),
5. 10763326 - Middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack (2020-09-01),
6. 10741559 - Spacer for trench epitaxial structures (2020-08-11),
7. 10699951 - Self-aligned low dielectric constant gate cap and a method of forming the same (2020-06-30),
8. 10629721 - Contact resistance reduction for advanced technology nodes (2020-04-21),
9. 10396200 - Method and structure of improving contact resistance for passive and long channel devices (2019-08-27),
10. 10361203 - FET trench dipole formation (2019-07-23),
11. 10355080 - Semiconductor structures including middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack (2019-07-16),
12. 10347633 - Spacer for trench epitaxial structures (2019-07-09),
13. 10347632 - Forming spacer for trench epitaxial structures (2019-07-09),
14. 10347628 - Simultaneously fabricating a high voltage transistor and a FinFET (2019-07-09),
15. 10325848 - Self-aligned local interconnect technology (2019-06-18),

Title: The Innovative Journey of Charan V V S Surisetty

Introduction: Charan V V S Surisetty is a talented inventor based in Clifton Park, NY (US) known for his groundbreaking contributions to the field of technology and innovation.

Latest Patents: Charan V V S Surisetty holds several patents in various technological domains, showcasing his versatility and creativity in inventing new solutions to complex problems.

Career Highlights: With a strong background in engineering and a passion for innovation, Charan V V S Surisetty has had a successful career marked by numerous achievements in the development of cutting-edge technologies.

Collaborations: Throughout his career, Charan V V S Surisetty has collaborated with leading research institutions, universities, and companies to bring his inventions to life, demonstrating his ability to work effectively in multidisciplinary teams.

Conclusion: Charan V V S Surisetty's dedication to innovation and his relentless pursuit of technological advancement make him a prominent figure in the world of inventors, with a bright future ahead in shaping the future of technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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