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For the Inventor, By the Inventor

Fremont, CA, United States of America

Chan-Chi Jason Cheng

USPTO Granted Patents = 18

Average Co-Inventor Count = 3.2

ph-index = 7

Forward Citations = 308(Granted Patents)


Location History:

  • San Jose, CA (US) (1992 - 1994)
  • Shanghai, CN (2011)
  • Fremont, CA (US) (2004 - 2013)

Company Filing History:

goldMedal18 out of 755 
 
Lattice Semiconductor Corporation
 patents

Years Active: 1992-2013

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18 patents (USPTO):Explore Patents
1. 8370691 - Testing of soft error detection logic for programmable logic devices (2013-02-05),
2. 8065574 - Soft error detection logic testing systems and methods (2011-11-22),
3. 8058898 - Compression and decompression of configuration data using repeated data frames (2011-11-15),
4. 7902865 - Compression and decompression of configuration data using repeated data frames (2011-03-08),
5. 7746107 - Redundant configuration memory systems and methods (2010-06-29),
6. 7663401 - Multiplexer initialization systems and methods (2010-02-16),
7. 7598765 - Redundant configuration memory systems and methods (2009-10-06),
8. 7576563 - High fan-out signal routing systems and methods (2009-08-18),
9. 7573291 - Programmable logic device with enhanced logic block architecture (2009-08-11),
10. 7295035 - Programmable logic device with enhanced logic block architecture (2007-11-13),
11. 6986004 - FIFO memory with programmable data port widths (2006-01-10),
12. 6879182 - CPLD with multi-function blocks and distributed memory (2005-04-12),
13. 6861871 - Cascaded logic block architecture for complex programmable logic devices (2005-03-01),
14. 6828823 - Non-volatile and reconfigurable programmable logic devices (2004-12-07),
15. 5336951 - Structure and method for multiplexing pins for in-system programming (1994-08-09),

Title: Innovations by Chan-Chi Jason Cheng

Introduction

Chan-Chi Jason Cheng is a prominent inventor based in Fremont, CA, known for his significant contributions to the field of programmable logic devices. With a total of 18 patents to his name, Cheng has made remarkable advancements in technology that enhance the reliability and functionality of electronic devices.

Latest Patents

One of his latest patents focuses on the "Testing of soft error detection logic for programmable logic devices." This invention involves a programmable logic device (PLD) equipped with configuration memory that includes soft error detection (SED) logic. The SED logic is designed to check for errors in the data stored by the configuration memory. It calculates a present data value for comparison with a pre-calculated data value, ensuring the integrity of the stored information. Another notable patent is related to "Soft error detection logic testing systems and methods." This invention describes a PLD that includes multiple configuration memory cells, with at least one functioning as random access memory. The soft error detection logic checks for errors in the data values stored, thereby enhancing the reliability of the device.

Career Highlights

Chan-Chi Jason Cheng has established himself as a key figure in the technology sector, particularly through his work at Lattice Semiconductor Corporation. His innovative patents have contributed to the advancement of programmable logic devices, making them more efficient and reliable.

Collaborations

Cheng has collaborated with notable colleagues such as Ju Shen and Om P Agrawal, further enriching his work and contributions to the field.

Conclusion

Chan-Chi Jason Cheng's innovative work in programmable logic devices has significantly impacted the technology landscape. His patents reflect a commitment to enhancing device reliability and functionality, marking him as a leading inventor in his field.

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