For the Inventor, By the Inventor

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Hillsboro, OR, United States of America

Lattice Semiconductor Corporation

Calculating rank

USPTO Granted Patents = 765

% Expired Patents = 6.8

EPO Patents = 56

Trademarks = 29

Forward Citations = 7,804

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566 inventors (with patents filed for the assignee):

Om P Agrawal (66 out of 143 patents)

Ju Shen (37 out of 50 patents)

William B Andrews (34 out of 34 patents)

4. John Schadt (33 out of 34 patents)

5. Sunil D Mehta (31 out of 96 patents)

6. Bradley A Sharpe-Geisler (31 out of 104 patents)

7. Howard H Tang (31 out of 38 patents)

8. Satwant Singh (30 out of 38 patents)

9. Brad Sharpe-Geisler (28 out of 30 patents)

10. Fulong Zhang (28 out of 28 patents)

11. Hoon Choi (26 out of 44 patents)

12. Cyrus Y Tsui (26 out of 26 patents)

13. Wei Han (24 out of 29 patents)

14. Zheng Chen (22 out of 22 patents)

15. Albert L Chan (21 out of 21 patents)

Core Competencies:

Clock Insertion Delay

Multi-Mode Look-Up Table

Low Latency Interrupts

Cryptographic Hardware

Secure Boot

Adaptive Processing

Non-Volatile Memory

Data Recovery

Audio Signal Transmission

Hysteresis Control

Power Supply Regulation

Error Detection

765 patents: Sort by Forward Citations

1. 12769851 - Parallel processing systems and methods for facilitating bitstream security (2026-10-20),

2. 12732191 - High-speed multi-mode logic block with combined outputs for programmable logic devices (2026-09-08),

3. 12675421 - Artificial intelligence memory architecture systems and methods (2026-07-07),

4. 12665697 - Communication systems and methods (2026-06-23),

5. 12634106 - Serdes lane control bonding systems and methods (2026-05-19),

6. 12597931 - Clock insertion delay systems and methods (2026-04-07),

7. 12597930 - Multi-mode look-up table with flexible routing for programmable logic device systems and methods (2026-04-07),

8. 12566944 - Low latency interrupt alerts for artificial neural network systems and methods in data stream processing (2026-03-03),

9. 12561264 - Scalable data structure for aggregating BMC input and output over serdes for data center and server nodes system and method (2026-02-24),

10. 12512143 - Dual power supplied memory cells and deterministic reset thereof for programmable logic devices (2025-12-30),

11. 12445132 - Cryptographic hardware sharing systems and methods (2025-10-14),

12. 12417319 - Multi-chip secure and programmable systems and methods (2025-09-16),

13. 12374416 - Programmable linear-feedback shift register systems and methods (2025-07-29),

14. 12373117 - Selectively powered embedded memory systems and methods (2025-07-29),

15. 12316774 - Information leakage mitigation associated with elliptic curve operations (2025-05-27),

Company Overview

Lattice Semiconductor Corporation, headquartered in Hillsboro, Oregon, specializes in the development and manufacturing of programmable logic devices. The company focuses on innovative technologies such as clock insertion delay, multi-mode look-up tables, and low latency interrupts, catering to a diverse range of applications. Lattice is also recognized for its advancements in cryptographic hardware, secure boot solutions, adaptive processing, non-volatile memory, and data recovery, positioning itself as a key player in the semiconductor industry.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 27 2026

765 Patents

#2 in Hillsboro, OR

#5 in Oregon

#660 in US

#1,305 in the World

Hillsboro, OR, United States of America

Lattice Semiconductor Corporation

Forward Citations = 7,804

566 inventors:

Om P Agrawal (66 out of 143 patents)

Ju Shen (37 out of 50 patents)

William B Andrews (34 out of 34 patents)

4. John Schadt (33 out of 34 patents)

5. Sunil D Mehta (31 out of 96 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Lattice Semiconductor Corporation. Retrieved from https://idiyas.com/company/lattice-semiconductor

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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