The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 19, 2026
Filed:
Apr. 04, 2024
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Choon Yee Tan, Bukit Mertajam, MY;
Sze Yin Lee, Bayan Lepas, MY;
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Abstract
Various techniques are provided to configure serializer/deserializer (SerDes) lanes in one or more SerDes quads into configurable groups using a bonded link. The configuration registers may configure the SerDes lanes into the configurable groups. A lane bonding control module in each SerDes quad may link the signals, including control signals, that travel within each configurable group. To synchronize the control signals, the lane bonding control module may include one or more flops that introduce a fixed time delay for control signals that travel between SerDes quads, and pipe stage match modules that introduce a variable time delay to match the fixed time delay caused by the flops. Once synchronized, the control signals arrive at different SerDes lanes in the configurable group at the same clock cycle.