The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 07, 2026
Filed:
May. 15, 2024
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Satwant Singh, Fremont, CA (US);
Patrick J. Crotty, San Jose, CA (US);
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Abstract
Various techniques are provided for implementing one or more multi-mode look-up tables (LUTs) in programmable logic devices (PLDs). In one example, a PLD includes a multi-mode LUT. The comprising: a plurality of input nodes configured to receive a plurality of input signals; wherein the multi-mode LUT is configurable to selectively operate in a first mode as a single LUT or in a second mode as dual LUTs and generate a plurality of output signals in accordance with one or more logic functions in response to the input signals; and a plurality of output nodes configured to provide the plurality of output signals simultaneously to routing resources of the PLD.