The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2026

Filed:

Mar. 01, 2019
Applicant:

Lattice Semiconductor Corporation, Portland, OR (US);

Inventor:

Ronald L. Cline, San Jose, CA (US);

Assignee:

Lattice Semiconductor Corporation, Hillsboro, OR (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 20/00 (2019.01); G06F 9/38 (2018.01); G06F 18/214 (2023.01); G06N 3/02 (2006.01); G06N 3/048 (2023.01); G06N 3/08 (2023.01); G06N 5/04 (2023.01);
U.S. Cl.
CPC ...
G06N 3/08 (2013.01); G06F 9/3877 (2013.01); G06F 18/214 (2023.01); G06N 5/04 (2013.01);
Abstract

Various techniques are provided for providing neural networks with increased efficiency. In one example, a system includes a first artificial neural network (ANN), a second ANN, and a logic device. The first ANN is configured to receive a first plurality of data inputs associated with a data stream and process the first data inputs to generate a first inference output after a first latency. The second ANN is configured to receive a second plurality of data inputs associated with the data stream and process the second data inputs to generate a second inference output after a second latency less than the first latency. The logic device is configured to receive the second inference output before the first inference output is generated. Additional systems and methods are also provided.


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