Cascaded logic block architecture for complex programmable logic devices

Abstract

Cascadable logic block architectures are disclosed for programmable logic devices, such as for high density and high performance complex programmable logic devices. The logic block architectures provide, for example, clusters or groups of logic blocks that may have cascadable inputs and/or product terms to provide flexible logic width and/or depth capability. The logic block architecture may, for example, be implemented in conjunction with a multi-stage interconnect architecture to provide array fuse density and/or interconnect fuse density savings compared to conventional architectures.