The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 18, 2009
Filed:
Feb. 06, 2007
Qin Wei, San Jose, CA (US);
Chan-chi Jason Cheng, Fremont, CA (US);
Brad Sharpe-geisler, San Jose, CA (US);
Ting Yew, San Jose, CA (US);
Qin Wei, San Jose, CA (US);
Chan-Chi Jason Cheng, Fremont, CA (US);
Brad Sharpe-Geisler, San Jose, CA (US);
Ting Yew, San Jose, CA (US);
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Abstract
Systems and methods are disclosed herein to provide high fan-out signal routing. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of logic blocks; an interconnect structure adapted to route signals among the logic blocks; and a secondary routing network adapted to route signals among the logic blocks. The secondary routing network may include a plurality of horizontal splines adapted to route signals within the programmable logic device; a plurality of vertical spline taps adapted to route signals within the programmable logic device; a plurality of common interface blocks adapted to route signals between the horizontal splines and the vertical spline taps; and a plurality of horizontal secondary branches adapted to route signals from the vertical spline taps to the logic blocks.