The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 16, 2010
Filed:
Nov. 03, 2006
Chi Minh Nguyen, San Jose, CA (US);
Chan-chi Jason Cheng, Fremont, CA (US);
Timothy S. Swensen, Santa Clara, CA (US);
Giai Trinh, Milpitas, CA (US);
Yi Chiang, San Jose, CA (US);
Chi Minh Nguyen, San Jose, CA (US);
Chan-Chi Jason Cheng, Fremont, CA (US);
Timothy S. Swensen, Santa Clara, CA (US);
Giai Trinh, Milpitas, CA (US);
Yi Chiang, San Jose, CA (US);
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Abstract
A programmable logic device, in accordance with an embodiment of the present invention, includes a plurality of multiplexers, having fuse input terminals and input signal terminals, and a plurality of associated fuses providing fuse signals to the fuse input terminals to control selection of the input signal terminals. The fuses in a first state select a first input signal terminal of the input signal terminals, with a first multiplexer from the plurality of multiplexers receiving a first logic level signal at the first input signal terminal and providing the first logic level signal to the first input signal terminal of a first set of the plurality of multiplexers. The fuses associated with the first set are adapted to be programmed before the fuses associated with the first multiplexer.