The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 13, 2007

Filed:

Aug. 09, 2005
Applicants:

OM Agrawal, Los Altos, CA (US);

Manish Garg, San Jose, CA (US);

Chan-chi Jason Cheng, Fremont, CA (US);

Satwant Singh, Fremont, CA (US);

Ju Shen, San Jose, CA (US);

Inventors:

Om Agrawal, Los Altos, CA (US);

Manish Garg, San Jose, CA (US);

Chan-Chi Jason Cheng, Fremont, CA (US);

Satwant Singh, Fremont, CA (US);

Ju Shen, San Jose, CA (US);

Assignee:

Lattice Semiconductor Corporation, Hillsboro, OR (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/177 (2006.01);
U.S. Cl.
CPC ...
Abstract

In one embodiment of the invention, a programmable logic block within a programmable logic device includes: a plurality of lookup tables, each lookup table providing a combinatorial output signal; and a plurality of registers, each register being adapted to register a selected one of the combinatorial output signals, wherein the number of registers is less than the number of lookup tables.


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