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Hsinchu, Taiwan

Texas Instruments-Acer Incorporated

USPTO Granted Patents = 134

Forward Citations = 2,227

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12 inventors (with patents filed for the assignee):

Shye-Lin Wu (130 out of 203 patents)

Jonathan Yen-Ping Chou (2 out of 2 patents)

Peter Kuo-Yuan Hsu (2 out of 2 patents)

4. Li-Ping Huang (1 out of 26 patents)

5. Cheng-Geng Jan (1 out of 52 patents)

6. Hsin-Tang Liu (1 out of 2 patents)

7. Jiahn-Rong Gau (1 out of 7 patents)

8. Tsu Chu Wu (1 out of 1 patent)

9. Cheng-Nan Lee (1 out of 1 patent)

10. Shye Lin Wu (1 out of 1 patent)

11. Tseng Te Lun (1 out of 1 patent)

12. Tsun-Chu Wu (1 out of 1 patent)

Core Competencies:

CMOS Transistors

Ultra-Short Channel MOSFETs

Flash Memories

DRAM Capacitors

Self-Aligned Silicide

High Density Memories

Buried Contact Structures

Synchronous DRAM

Trench Capacitors

Nonvolatile Memories

Electromagnetic Signal Receiving

Dual Threshold Circuits

134 patents: Sort by Forward Citations

1. 6649308 - Ultra-short channel NMOSFETS with self-aligned silicide contact (2003-11-18),

2. 6548362 - Method of forming MOSFET with buried contact and air-gap gate structure (2003-04-15),

3. 6432785 - Method for fabricating ultra short channel PMOSFET with buried source/drain junctions and self-aligned silicide (2002-08-13),

4. 6331456 - Fipos method of forming SOI CMOS structure (2001-12-18),

5. 6316316 - Method of forming high density and low power flash memories with a high capacitive-coupling ratio (2001-11-13),

6. 6294797 - MOSFET with an elevated source/drain (2001-09-25),

7. 6294416 - Method of fabricating CMOS transistors with self-aligned planarization twin-well by using fewer mask counts (2001-09-25),

8. 6284612 - Process to fabricate ultra-short channel MOSFETs with self-aligned silicide contact (2001-09-04),

9. 6265263 - Method for forming a DRAM capacitor with porous storage node and rugged sidewalls (2001-07-24),

10. 6265259 - Method to fabricate deep sub-&mgr;m CMOSFETs (2001-07-24),

11. 6259130 - High density flash memories with high capacitive-couping ratio and high speed operation (2001-07-10),

12. 6255167 - Method of forming high density buried bit line flash EEPROM memory cell with a shallow trench floating gate (2001-07-03),

13. 6214696 - Method of fabricating deep-shallow trench isolation (2001-04-10),

14. 6211556 - Eliminating buried contact trench in MOSFET devices having self-aligned silicide (2001-04-03),

15. 6211016 - Method for forming high density nonvolatile memories with high capacitive-coupling ratio (2001-04-03),

Texas Instruments-Acer Incorporated is a global semiconductor design and manufacturing company. They offer a wide range of products, including analog, embedded processing, and digital signal processing solutions. Their innovative technologies are used in various industries, such as automotive, industrial, communications, and consumer electronics.

This text is generated by artificial intelligence and may not be accurate.

Company Badge

USPTO Data Jan 1 1976 - Sep 29 2026

Texas Instruments-Acer Incorporated

134 Patents

#53 in Hsinchu

#182 in Taiwan

#6,009 in the World

Hsinchu, Taiwan

Texas Instruments-Acer Incorporated

Forward Citations = 2,227

12 inventors:

Shye-Lin Wu (130 out of 203 patents)

Jonathan Yen-Ping Chou (2 out of 2 patents)

Peter Kuo-Yuan Hsu (2 out of 2 patents)

4. Li-Ping Huang (1 out of 26 patents)

5. Cheng-Geng Jan (1 out of 52 patents)

Please report any incorrect information to [email protected]

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