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Hsinchu, Taiwan

Texas Instruments-Acer Incorporated

USPTO Granted Patents = 134

Forward Citations = 2,227

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12 inventors (with patents filed for the assignee):

Shye-Lin Wu (130 out of 203 patents)

Jonathan Yen-Ping Chou (2 out of 2 patents)

Peter Kuo-Yuan Hsu (2 out of 2 patents)

4. Li-Ping Huang (1 out of 26 patents)

5. Cheng-Geng Jan (1 out of 52 patents)

6. Hsin-Tang Liu (1 out of 2 patents)

7. Jiahn-Rong Gau (1 out of 7 patents)

8. Tsu Chu Wu (1 out of 1 patent)

9. Cheng-Nan Lee (1 out of 1 patent)

10. Shye Lin Wu (1 out of 1 patent)

11. Tseng Te Lun (1 out of 1 patent)

12. Tsun-Chu Wu (1 out of 1 patent)

Core Competencies:

CMOS Transistors

Ultra-Short Channel MOSFETs

Flash Memories

DRAM Capacitors

Self-Aligned Silicide

High Density Memories

Buried Contact Structures

Synchronous DRAM

Trench Capacitors

Nonvolatile Memories

Electromagnetic Signal Receiving

Dual Threshold Circuits

134 patents: Sort by Forward Citations

1. 6649308 - Ultra-short channel NMOSFETS with self-aligned silicide contact (2003-11-18),

2. 6548362 - Method of forming MOSFET with buried contact and air-gap gate structure (2003-04-15),

3. 6432785 - Method for fabricating ultra short channel PMOSFET with buried source/drain junctions and self-aligned silicide (2002-08-13),

4. 6331456 - Fipos method of forming SOI CMOS structure (2001-12-18),

5. 6316316 - Method of forming high density and low power flash memories with a high capacitive-coupling ratio (2001-11-13),

6. 6294797 - MOSFET with an elevated source/drain (2001-09-25),

7. 6294416 - Method of fabricating CMOS transistors with self-aligned planarization twin-well by using fewer mask counts (2001-09-25),

8. 6284612 - Process to fabricate ultra-short channel MOSFETs with self-aligned silicide contact (2001-09-04),

9. 6265263 - Method for forming a DRAM capacitor with porous storage node and rugged sidewalls (2001-07-24),

10. 6265259 - Method to fabricate deep sub-&mgr;m CMOSFETs (2001-07-24),

11. 6259130 - High density flash memories with high capacitive-couping ratio and high speed operation (2001-07-10),

12. 6255167 - Method of forming high density buried bit line flash EEPROM memory cell with a shallow trench floating gate (2001-07-03),

13. 6214696 - Method of fabricating deep-shallow trench isolation (2001-04-10),

14. 6211556 - Eliminating buried contact trench in MOSFET devices having self-aligned silicide (2001-04-03),

15. 6211016 - Method for forming high density nonvolatile memories with high capacitive-coupling ratio (2001-04-03),

Company Overview

Texas Instruments-Acer Incorporated, based in Hsinchu, Taiwan, specializes in advanced semiconductor technologies, particularly in CMOS technology. The company focuses on the development and manufacturing of CMOS transistors, ultra-short channel MOSFETs, and high-density memory solutions, including flash memories and DRAM capacitors. Their expertise extends to innovative structures such as self-aligned silicide and buried contact structures, positioning them as a key player in the semiconductor industry, particularly in memory and logic device applications.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 20 2026

134 Patents

#54 in Hsinchu

#183 in Taiwan

#6,022 in the World

Hsinchu, Taiwan

Texas Instruments-Acer Incorporated

Forward Citations = 2,227

12 inventors:

Shye-Lin Wu (130 out of 203 patents)

Jonathan Yen-Ping Chou (2 out of 2 patents)

Peter Kuo-Yuan Hsu (2 out of 2 patents)

4. Li-Ping Huang (1 out of 26 patents)

5. Cheng-Geng Jan (1 out of 52 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Texas Instruments-Acer Incorporated. Retrieved from https://idiyas.com/company/texas-instruments-acer

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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