Method for forming a dram capacitor with porous storage node and rugged sidewalls

Abstract

The method for forming a DRAM capacitor can include the following steps. First, a first dielectric layer is formed on a semiconductor substrate, followed by the formation of a second dielectric layer on the first dielectric layer, and the formation of a third dielectric layer on the second dielectric layer. Next, the first, second, and third dielectric layers are patterned to form a contact hole therein. A doped polysilicon layer is then formed within the contact hole and over the third dielectric layer, followed by the formation of a fourth dielectric layer over the doped polysilicon layer. A patterning step patterns the fourth dielectric layer and the doped polysilicon layer to define a storage node. A hemispherical grained silicon layer is then formed on the fourth dielectric layer, on sidewalls of the storage node, and on the third dielectric layer. The hemispherical grained silicon layer is etched to define a plurality of cavities between grains of the hemispherical grained silicon layer and to expose the fourth dielectric layer through the plurality of cavities. The fourth dielectric layer and the doped polysilicon layer underlying the cavities are then etched to form a porous storage node. The fourth dielectric layer and the third dielectric layer are removed, followed by the formation of a fifth dielectric layer on the porous storage node and the substrate. Finally, a conductive layer is formed on the fifth dielectric layer.