The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 18, 2001
Filed:
May. 04, 1998
Shye-Lin Wu, Hsinchu, TW;
Texas Instruments - Acer Incorporated, Hsinchu, TW;
Abstract
The present invention discloses a method to form CMOS transistors for high speed and lower power applications. A high energy and low dose phosphorous is implanted in a silicon substrate to fabricate an N-well after a pad oxide layer and a silicon nitride layer is formed. After a thick field oxide is formed by using a high temperature steam oxidation process, another high energy and low dose multiple boron implantation is then performed to fabricate a buried heavily boron doped region. A rapid thermal processing (RTP) system is following used to activate the boron dopant to form buried p+ layer and to recover the implanted damages. All the field oxide films are then removed by using a diluted HF or BOE solution. After porous silicon is obtained via anodic electrochemical dissolution in the HF solution, the porous silicon is then thermally oxidized to form the separate n-type silicon islands. Next, a thick CVD oxide film is deposited and then etched back to planarize device surface. Selectively boron ion implantation is used to convert n-type silicon islands into p-type silicon islands. Finally, CMOS transistors can be fabricated on the silicon islands.