Method for fabricating ultra short channel pmosfet with buried source/drain junctions and self-aligned silicide

Abstract

The proposed method of the present invention forms MOSFETs with improved short channel effects and operating speeds over conventional devices. The method for fabricating MOSFETs includes the following steps. At first, isolation regions are formed on a semiconductor substrate and a gate insulating layer is formed on the substrate. A first conductive layer is then formed on the gate insulating layer and a first dielectric layer is formed on the first conductive layer. A removing process is performed to remove portions of the gate insulating layer, the first conductive layer and the first dielectric layer to define a gate structure. A layer formation step is carried out to form a thermal oxide layer on the substrate and on sidewalls the first conductive layer. Doped dielectric sidewall spacers are then formed on sidewalls of the gate structure. A removing step is carried out to remove portions of the thermal oxide layer uncovered by the doped dieletric sidewall spacers. Next, the first dielectric layer is removed and a doped silicon layer is selectively deposited on the first conductive layer and on exposed regions of substrate surface. A first metal layer is then formed on the substrate. A thermal process is carried out to drive in dopants in the doped dielectric sidewall spacers and the doped silicon layer, and to convert portions of the first metal layer into a metal silicide layer lying over the doped silicon layer. A removing step then removes unreacted portions of the first metal layer.