The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 10, 2001
Filed:
Mar. 09, 1999
Shye-Lin Wu, Hsinchu, TW;
Texas Instruments - Acer Incorporated, Hsinchu, TW;
Abstract
The device includes a gate oxide formed on a semiconductor substrate. Oxide regions are respectively formed on the substrate and adjacent to the gate oxide. Textured oxides are formed on the substrate, between the gate oxide and the oxide regions. A floating gate consists of a first polysilicon portion, second polysilicon portions and a third portion that is composed of hemisperical grained silicon (HSG-Si). The first polysilicon portion is formed on the gate oxide. Isolations are formed on the side walls of the first polysilicon portion. The second polysilicon portions are respectively formed next to the isolations and over a portion of the oxide regions. The HSG-Si is formed on the upper surface of the first polysilicon portion and the second polysilicon portions. A dielectric layer is formed on the HSG-Si of the floating gate. A control gate is formed on the dielectric layer. The doped regions are formed in the substrate and under the textured oxides and the oxide regions.