Method of forming high density and low power flash memories with a high capacitive-coupling ratio

Abstract

The method for forming flash memory includes the following steps. At first, a semiconductor substrate with an isolation region formed upon is provided. The semiconductor substrate has a pad oxide layer and a first nitride layer formed over. A portion of the first nitride layer and of the pad oxide layer are removed to define a gate region. A first oxide layer is formed and then a sidewall structure is formed. The semiconductor substrate is doped with first type dopants. A first thermal process is performed to form a second oxide layer and drive in the first type dopants. The sidewall structure and the first nitride layer are then removed, and the first oxide layer is removed to expose a portion of the substrate under the first oxide layer. Silicon grains are formed on the pad oxide layer, the exposed portion of substrate, and the second oxide layer. The exposed portion of the substrate is then etched to leave a rugged surface on the exposed portion of the substrate. A second thermal process is performed to form a tunnel oxide layer on the rugged surface. A first conductive layer is formed over the substrate and a portion of the first conductive layer is removed to define a floating gate. A dielectric layer is formed over the semiconductor substrate and a second conductive layer is then formed over as a control gate.