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Mountain View, CA, United States of America

Synopsis Incorporated

USPTO Granted Patents = 13

Forward Citations = 118

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39 inventors (with patents filed for the assignee):

Albert Wang (2 out of 2 patents)

Peter Macliesh (2 out of 2 patents)

Benjamin Chen (2 out of 2 patents)

4. Ruifeng Guo (1 out of 23 patents)

5. Brian Archer (1 out of 4 patents)

6. Yanjun Ma (1 out of 36 patents)

7. John Pasternak (1 out of 3 patents)

8. Pratik Mahajan (1 out of 4 patents)

9. Sandeep Jana (1 out of 4 patents)

10. Hongchuan Li (1 out of 1 patent)

11. Aydin Osman Balkan (1 out of 1 patent)

12. Arunava Saha (1 out of 5 patents)

13. Kevin Chau (1 out of 2 patents)

14. Xiaolei Cai (1 out of 3 patents)

15. Philippe Francis Sarrazin (1 out of 3 patents)

13 patents: Sort by Forward Citations

1. 10706208 - Priority aware balancing of memory usage between geometry operation and file storage (2020-07-07),

2. 10592624 - Efficient mechanism of fault qualification using formal verification (2020-03-17),

3. 10528692 - Cell-aware defect characterization for multibit cells (2020-01-07),

4. 9432003 - Multi-bit standard cells for consolidating transistors with selective sourcing (2016-08-30),

5. 8707235 - Techniques for use with automated circuit design and simulations (2014-04-22),

6. 8407650 - Method for repeated block modification for chip routing (2013-03-26),

7. 7843032 - Radio frequency identification device electrostatic discharge management (2010-11-30),

8. 7415694 - Graph based phase shift lithography mapping method and apparatus (2008-08-19),

9. 6810373 - Method and apparatus for modeling using a hardware-software co-verification environment (2004-10-26),

10. 6295517 - Method and apparatus for adaptively or selectively choosing event-triggered cycle-based simulation or oblivious-triggered cycle-based simulation on a cluster-by-cluster basis (2001-09-25),

11. 6167561 - Method and apparatus for entry of timing constraints (2000-12-25),

12. 616756 - Method and apparatus for entry of timing constraints (2000-12-26),

13. 5673295 - Method and apparatus for generating and synchronizing a plurality of (1997-09-30),

Company Overview

Synopsys Incorporated is a leading provider of electronic design automation (EDA) software and services, specializing in the development of advanced semiconductor design and verification solutions. The company focuses on enabling innovation in various technology domains, including integrated circuit design, software security, and quality assurance. Headquartered in Mountain View, California, Synopsys serves a global clientele, empowering organizations to enhance their product development processes and accelerate time-to-market through its comprehensive suite of tools and expertise.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 20 2026

13 Patents

#204 in Mountain View, CA

#5,661 in California

#23,854 in US

#45,081 in the World

Mountain View, CA, United States of America

Synopsis Incorporated

Forward Citations = 118

39 inventors:

Albert Wang (2 out of 2 patents)

Peter Macliesh (2 out of 2 patents)

Benjamin Chen (2 out of 2 patents)

4. Ruifeng Guo (1 out of 23 patents)

5. Brian Archer (1 out of 4 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Synopsis Incorporated. Retrieved from https://idiyas.com/company/synopsis

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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