The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 26, 2013
Filed:
May. 30, 2008
Jacob Avidan, Los Altos, CA (US);
Sandeep Grover, Sunnyvale, CA (US);
Roger Carpenter, Palo Alto, CA (US);
Philippe Sarrazin, San Jose, CA (US);
Jacob Avidan, Los Altos, CA (US);
Sandeep Grover, Sunnyvale, CA (US);
Roger Carpenter, Palo Alto, CA (US);
Philippe Sarrazin, San Jose, CA (US);
Synopsis, Inc., Mountain View, CA (US);
Abstract
In various embodiments, each possible different instance of a repeated block can be concurrently modified for chip routing. Repeated blocks can be implemented where all instances of a repeated block are identical or substantially identical. Pin placement may be determined based on analysis of the I/O for all instances. The pin placement may be generated to be identical or substantially similar for all instances. Flyover blockages can be designed into repeated blocks to enable the global router to wire through the repeated block. Buffers and associated pins can be inserted into repeated block within the flyover space where the global router wires to the needed buffer through area pins.