Method and apparatus for generating and synchronizing a plurality of

Abstract

A hardware interface generates and synchronizes precisely timed digital signals. The hardware interface receives data bits and associated timing information for application to a Hardware Modeling Element (HME). Preferably there are at least two modules, each including a clock generating circuit which has an input for receiving a master clock signal, a divider circuit for generating therefrom a plurality of evenly timed internal clock signals, wherein a first one of the internal clock signals rises at the same time as the master clock signal, and a phase adjusting circuit for receiving a feedback control signal for adjusting a phase delay in accordance with a sensed throughput delay. Each module also includes a timing multiplexer which receives the internal clock signals and each having a plurality of data channels, each having approximately the same throughput delay. Each data channel also has an input for receiving a data bit, a controller for receiving the timing information which allows selection of the one internal clock signal which most closely matches the timing information, and an output port coupled to the HME. The timing multiplexer also has a dummy channel from which the sensed delay is determined. The sensed delay approximates the throughput delay. The dummy channel receives the first one of the internal clock signals and provides the feedback control signal. Finally, the hardware interface apparatus includes a timing adjustment control circuit for selectively delaying the output signal in one timing multiplexer to compensate for a slower throughput delay in another multiplexer.