Method and apparatus for adaptively or selectively choosing event-triggered cycle-based simulation or oblivious-triggered cycle-based simulation on a cluster-by-cluster basis

Abstract

A simulation architecture and method having four major steps. Firstly, an input circuit description to be simulated is compiled into an initial circuit compilation as follows. The input circuit description is translated into an initial register transfer level (RTL) network representation comprised of sequential and/or combinational objects. Next, translation of the RTL network into a network of clusters is accomplished. In general, a cluster is a region of the circuit which has uniform simulation activity. The initial clustering process, by default, chooses an simulation mode for all clusters known as event-triggered cycle-based. The other possible simulation mode for a cluster, in accordance with the present invention, is oblivious-triggered cycle-based. The first major step completes with translating the network of clusters into simulatable object code which includes additional object code that generates activity data regarding each cluster during a simulation. In the second major step, part of the complete suite of test vectors, such portion being known as profile test vector subset, is simulated upon the object code of the initial circuit compilation to produce activity data. For the third major step the input circuit description to be simulated is compiled again, but is optimized utilizing the activity data. The activity data is used to decide which clusters should either be merged into larger event-triggered cycle-based clusters or individually switched from event-triggered cycle-based simulation to oblivious-triggered cycle-based simulation. The simulation mode is chosen, or clusters are merged, on a cluster-by-cluster basis, to optimize simulation efficiency (and therefore minimize simulation time). Finally, in the fourth major step the optimized circuit compilation is simulated with the full suite of test vectors.