The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 07, 2020
Filed:
Oct. 31, 2018
Synopsys, Inc., Mountain View, CA (US);
Ruifeng Guo, Portland, OR (US);
Brian M. Archer, Mountain View, CA (US);
Kevin Chau, San Jose, CA (US);
Xiaolei Cai, Portland, OR (US);
Synopsis, Inc., Mountain View, CA (US);
Abstract
A cell-aware defect characterization method includes partitioning a multibit cell netlist file into multiple single-bit partition netlist files, and then generating a cell-aware test model for each partition netlist file. Partitioning is performed such that each partition netlist file includes a corresponding flip-flop along with input, output and control pins that are operably coupled to the input, output and control terminals of the corresponding flip-flop, and all active, passive and parasitic circuit elements that are coupled in the signal paths extending between the corresponding flip-flop and the input/output/control pins. Shared resources (e.g., clock or scan select pins and associated signal lines) that are utilized by two or more flip-flops are included in each associated partition. The partitioning process is performed using either a structural back-tracing approach or a logic simulation approach.