For the Inventor, By the Inventor

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San Jose, CA, United States of America

Siliconix Incorporated

USPTO Granted Patents = 256

% Expired Patents = 1.6

EPO Patents = 13

Trademarks = 12

Forward Citations = 12,007

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128 inventors (with patents filed for the assignee):

Richard Kent Williams (100 out of 319 patents)

Mike F Chang (39 out of 50 patents)

Richard A Blanchard (34 out of 271 patents)

4. Mohamed N Darwish (33 out of 123 patents)

5. Fwu-Iuan Hshieh (31 out of 142 patents)

6. Hamza Yilmaz (26 out of 259 patents)

7. King Owyang (22 out of 30 patents)

8. Michael E Cornell (19 out of 57 patents)

9. Jun W Chen (19 out of 19 patents)

10. Adrian I Cogan (17 out of 50 patents)

11. Kyle Terrill (15 out of 72 patents)

12. Yueh-Se Ho (13 out of 102 patents)

13. Kuo-In Chen (11 out of 32 patents)

14. Dorman C Pitzer (11 out of 14 patents)

15. Kam Hong Lui (10 out of 15 patents)

Core Competencies:

Trench MOSFET

Power Semiconductor

Semiconductor Packaging

Field-Plate Design

Drain-Drift Region

High Density

Low On-Resistance

Bidirectional MOSFET

Thermal Management

Integrated Circuit

Voltage Clamping

Oxide Layer

256 patents: Sort by Forward Citations

1. 12635176 - Termination structure (2026-05-19),

2. 12224232 - Semiconductor package having side wall plating (2025-02-11),

3. 12211704 - Semiconductor package having side wall plating (2025-01-28),

4. 10483356 - Power semiconductor device with optimized field-plate design (2019-11-19),

5. 7795675 - Termination for trench MIS device (2010-09-14),

6. 7704836 - Method of fabricating super trench MOSFET including buried source electrode (2010-04-27),

7. 7557409 - Super trench MOSFET including buried source electrode (2009-07-07),

8. 7435650 - Process for manufacturing trench MIS device having implanted drain-drift region and thick bottom oxide (2008-10-14),

9. 7416947 - Method of fabricating trench MIS device with thick oxide layer in bottom of trench (2008-08-26),

10. 7394150 - Semiconductor package including die interposed between cup-shaped lead frame and lead frame having mesas and valleys (2008-07-01),

11. 7326995 - Trench MIS device having implanted drain-drift region and thick bottom oxide (2008-02-05),

12. 7291884 - Trench MIS device having implanted drain-drift region and thick bottom oxide (2007-11-06),

13. 7268032 - Termination for trench MIS device having implanted drain-drift region (2007-09-11),

14. 7238551 - Method of fabricating semiconductor package including die interposed between cup-shaped lead frame having mesas and valleys (2007-07-03),

15. 7233043 - Triple-diffused trench MOSFET (2007-06-19),

Company Overview

Siliconix Incorporated, based in San Jose, CA, specializes in the development and manufacturing of advanced trench MOSFET technology. The company focuses on power semiconductors that enhance efficiency and performance in various applications. Their expertise includes semiconductor packaging, field-plate design, and innovations in drain-drift region architecture, which contribute to high-density, low on-resistance, and bidirectional MOSFET solutions. Siliconix plays a crucial role in powering modern electronic devices and systems across multiple industries.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 20 2026

256 Patents

#51 in San Jose, CA

#356 in California

#1,682 in US

#3,415 in the World

San Jose, CA, United States of America

Siliconix Incorporated

Forward Citations = 12,007

128 inventors:

Richard Kent Williams (100 out of 319 patents)

Mike F Chang (39 out of 50 patents)

Richard A Blanchard (34 out of 271 patents)

4. Mohamed N Darwish (33 out of 123 patents)

5. Fwu-Iuan Hshieh (31 out of 142 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Siliconix Incorporated. Retrieved from https://idiyas.com/company/siliconix

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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