The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 03, 2007
Filed:
Nov. 23, 2004
Mohammed Kasem, Santa Clara, CA (US);
King Owyang, Atherton, CA (US);
Frank Kuo, Kaohsiung, TW;
Serge Robert Jaunay, Sunnyvale, CA (US);
Sen Mao, Kaohsiung, TW;
Oscar Ou, Kaohsiung, TW;
Peter Wang, Kaohsiung, TW;
Chang-sheng Chen, Santa Clara, CA (US);
Mohammed Kasem, Santa Clara, CA (US);
King Owyang, Atherton, CA (US);
Frank Kuo, Kaohsiung, TW;
Serge Robert Jaunay, Sunnyvale, CA (US);
Sen Mao, Kaohsiung, TW;
Oscar Ou, Kaohsiung, TW;
Peter Wang, Kaohsiung, TW;
Chang-Sheng Chen, Santa Clara, CA (US);
Siliconix incorporated, Santa Clara, CA (US);
Abstract
A semiconductor package includes a die that is interposed, flip-chip style, between an upper lead frame and a lower lead frame. The lower lead frame has contacts that are aligned with terminals on the bottom surface of the die. The upper lead frame contacts a terminal on the top side of the die, and the edges of the upper lead frame are bent downward around the edges of the die, giving the upper lead frame a cup shape. The edge of the upper lead frame contact another portion of the lower lead frame, so that all of the contacts of the package are coplanar and can be surface-mounted on a printed circuit board. The terminals of the die are electrically connected to the lead frames by means of solder layers. The thicknesses of the respective solder layers that connect the die to the lead frames are predetermined to optimize the performance of the package through numerous thermal cycles. This is done by fabricating the lower lead frame with a plurality of mesas and using a double solder reflow process.