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For the Inventor, By the Inventor

San Jose, CA, United States of America

Aplus Flash Technology, Inc.

Calculating rank
USPTO Granted Patents = 110

% Expired Patents = 47.3

Forward Citations = 2,277

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14 inventors (with patents filed for the assignee):

goldMedal Peter Wung Lee (109 out of 164 patents)

silverMedal Fu-Chang Hsu (80 out of 136 patents)

bronzeMedal Hsing-Ya Tsao (60 out of 79 patents)

4.  Han-Rei Ma (16 out of 19 patents)

5.  Vei-Han Chan (6 out of 49 patents)

6.  Koucheng Wu (6 out of 17 patents)

7.  Hung-Sheng Chen (6 out of 24 patents)

8.  Kesheng Wang (3 out of 3 patents)

9.  Mervyn Wong (3 out of 4 patents)

10.  Mike Hsinyih Chen (3 out of 3 patents)

11.  Tam Huu Tran (2 out of 3 patents)

12.  Wen-Tan Fan (1 out of 1 patent)

13.  Hsing-Ya Tsao (1 out of 1 patent)

14.  Fu-Change Hsu (1 out of 1 patent)


Core Competencies:
NAND Array Architecture
Concurrent Programming
Low Disturbance
Non-volatile Memory
Memory Cell Design
Hybrid NVM Design
EEPROM Integration
Voltage Flash Charger
Memory System
High Speed
Data-oriented Design
Flash Memory Array

110 patents:

1. 9666286 - Self-timed SLC NAND pipeline and concurrent program without verification (2017-05-30),
2. 9443579 - VSL-based VT-compensation and analog program scheme for NAND array without CSL (2016-09-13),
3. 9443578 - NAND array architecture for multiple simultaneous program and read (2016-09-13),
4. 9437306 - NAND array architecture for multiple simutaneous program and read (2016-09-06),
5. 9183940 - Low disturbance, power-consumption, and latency in NAND read and program-verify operations (2015-11-10),
6. 9177658 - 1T1b and 2T2b flash-based, data-oriented EEPROM design (2015-11-03),
7. 9177645 - 10T NVSRAM cell and cell operations (2015-11-03),
8. 9177644 - Low-voltage fast-write PMOS NVSRAM cell (2015-11-03),
9. 9171627 - Non-boosting program inhibit scheme in NAND design (2015-10-27),
10. 9087595 - Shielding 2-cycle half-page read and program schemes for advanced NAND flash design (2015-07-21),
11. 9063849 - Different types of memory integrated in one chip by using a novel protocol (2015-06-23),
12. 9019764 - Low-voltage page buffer to be used in NVM design (2015-04-28),
13. 9001583 - On-chip HV and LV capacitors acting as the second back-up supplies for NVSRAM auto-store operation (2015-04-07),
14. 9001545 - NOR-based BCAM/TCAM cell and array with NAND scalability (2015-04-07),
15. 8996785 - NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with serial interface (2015-03-31),
Company Overview
Aplus Flash Technology, Inc., based in San Jose, CA, specializes in the development and manufacturing of advanced NAND flash memory solutions. The company focuses on innovative technologies such as NAND array architecture, concurrent programming, and low disturbance techniques, which enhance the performance and reliability of non-volatile memory systems. Aplus is committed to advancing memory cell design and hybrid NVM design, integrating EEPROM technologies, and optimizing voltage flash charging to meet the evolving demands of the semiconductor industry.
Profile summary synthesized from public USPTO records and patent filings.

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USPTO Data Jan 1 1976 - Oct 20 2026

110 Patents

#106 in San Jose, CA

#791 in California

#3,480 in US

#7,166 in the World

San Jose, CA (US)
San Jose, CA, United States of America

Aplus Flash Technology, Inc.

Forward Citations = 2,277

14 inventors:

goldMedal Peter Wung Lee (109 out of 164 patents)

silverMedal Fu-Chang Hsu (80 out of 136 patents)

bronzeMedal Hsing-Ya Tsao (60 out of 79 patents)

4.  Han-Rei Ma (16 out of 19 patents)

5.  Vei-Han Chan (6 out of 49 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Aplus Flash Technology, Inc.. Retrieved from https://idiyas.com/company/aplus-flash-technology

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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