The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2015

Filed:

Apr. 20, 2013
Applicant:

Aplus Flash Technology, Inc, Fremont, CA (US);

Inventor:

Peter Wung Lee, Saratoga, CA (US);

Assignee:

Aplus Flash Technology, Inc., Fremont, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 16/26 (2006.01); G11C 16/04 (2006.01); G11C 11/56 (2006.01); G11C 16/24 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 16/26 (2013.01); G11C 16/0408 (2013.01); G11C 16/0483 (2013.01); G11C 11/5642 (2013.01); G11C 16/24 (2013.01); G11C 16/3427 (2013.01);
Abstract

The present invention provides a two-cycle half-page read scheme by dividing whole NAND array bit lines (BLs) into an odd-BL group and an even-BL group. During the half-plane reading of NAND cells in the odd(even)-BL group, the half-plane even(odd)-BL group acts as the shielding BLs to protect over the odd(even)-BL string reading so that each half-page read operation is substantially reliable and free from BL coupling noise effect. Additionally, each half-page read operation is preferably divided into 3 periods: the first being a bias-condition setup period of the selected WL and remaining control signals; the second being a pre-charge period for all BLs; and the third being a half-page flash data sensing period.


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