logo

For the Inventor, By the Inventor

Mountain View, CA, United States of America

Actel Corporation, Inc.


USPTO Granted Patents = 463

% Expired Patents = 23.1


Trademarks = 4

Forward Citations = 13,899

Loading Chart...
Loading Chart...

156 inventors (with patents filed for the assignee):

goldMedal John L McCollum (114 out of 159 patents)

silverMedal William C Plants (85 out of 111 patents)

bronzeMedal Gregory William Bakker (60 out of 63 patents)

4.  Jonathan W Greene (35 out of 61 patents)

5.  Jung-Cheun Lien (35 out of 35 patents)

6.  Sinan Kaptanoglu (34 out of 66 patents)

7.  Theodore M Speers (33 out of 35 patents)

8.  Frank W Hawley (30 out of 42 patents)

9.  Arunangshu Kundu (29 out of 31 patents)

10.  Khaled A El-Ayat (27 out of 28 patents)

11.  Fethi Dhaoui (25 out of 42 patents)

12.  Limin Zhu (23 out of 23 patents)

13.  Sheng Feng (23 out of 23 patents)

14.  King W Chan (22 out of 32 patents)

15.  Eddy C Huang (22 out of 35 patents)


Core Competencies:
FPGA Architecture
Non-volatile Memory
Programmable Logic
Integrated Circuits
Memory Cells
Microcontroller Systems
Signal Routing
Power Management
Delay Lines
Error Detection
Transistor Technology
Radiation Tolerance

463 patents:

1. 8570819 - Non-volatile memory array architecture optimized for hi-reliability and commercial markets (2013-10-29),
2. 8446170 - FPGA RAM blocks optimized for use as register files (2013-05-21),
3. 8415650 - Front to back resistive random access memory cells (2013-04-09),
4. 8320178 - Push-pull programmable logic device cell (2012-11-27),
5. 8289047 - Architecture and interconnect scheme for programmable logic circuits (2012-10-16),
6. 8269204 - Back to back resistive random access memory cells (2012-09-18),
7. 8269203 - Resistive RAM devices for programmable logic devices (2012-09-18),
8. 8258811 - Enhanced field programmable gate array (2012-09-04),
9. 8258567 - Non-volatile two-transistor programmable logic cell and array layout (2012-09-04),
10. 8255854 - Architecture and method for compensating for disparate signal rise and fall times by using polarity selection to improve timing and power in an integrated circuit (2012-08-28),
11. 8244791 - Fast carry lookahead circuits (2012-08-14),
12. 8191021 - Single event transient mitigation and measurement in integrated circuits (2012-05-29),
13. 8120955 - Array and control method for flash based FPGA cell (2012-02-21),
14. 8085064 - Logic module including versatile adder for FPGA (2011-12-27),
15. 8067959 - Programmable delay line compensated for process, voltage, and temperature (2011-11-29),
Company Overview
Actel Corporation, Inc. is a prominent player in the field of programmable logic devices, specializing in the development and manufacturing of advanced FPGA architectures and integrated circuits. The company focuses on innovative solutions that incorporate non-volatile memory, programmable logic, and microcontroller systems, catering to a diverse range of applications. With a strong emphasis on power management and signal routing technologies, Actel serves various industries, enhancing the capabilities of electronic systems globally from its headquarters in Mountain View, California.
Profile summary synthesized from public USPTO records and patent filings.

logo

Company Badge

USPTO Data Jan 1 1976 - Oct 13 2026

Actel Corporation, Inc. USPTO Patent Assignee Logo
463 Patents

#12 in Mountain View, CA

#225 in California

#1,037 in US

#2,060 in the World

Mountain View, CA (US)
Mountain View, CA, United States of America

Actel Corporation, Inc.

Forward Citations = 13,899

156 inventors:

goldMedal John L McCollum (114 out of 159 patents)

silverMedal William C Plants (85 out of 111 patents)

bronzeMedal Gregory William Bakker (60 out of 63 patents)

4.  Jonathan W Greene (35 out of 61 patents)

5.  Jung-Cheun Lien (35 out of 35 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Actel Corporation, Inc.. Retrieved from https://idiyas.com/company/actel

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…