The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2024

Filed:

Jun. 26, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Cheng-Ying Huang, Portland, OR (US);

Gilbert Dewey, Beaverton, OR (US);

Anh Phan, Beaverton, OR (US);

Nicole K. Thomas, Portland, OR (US);

Urusa Alaan, Hillsboro, OR (US);

Seung Hoon Sung, Portland, OR (US);

Christopher M. Neumann, Portland, OR (US);

Willy Rachmady, Beaverton, OR (US);

Patrick Morrow, Portland, OR (US);

Hui Jae Yoo, Portland, OR (US);

Richard E. Schenker, Portland, OR (US);

Marko Radosavljevic, Portland, OR (US);

Jack T. Kavalieros, Portland, OR (US);

Ehren Mannebach, Beaverton, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/775 (2006.01); H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
H01L 27/0924 (2013.01); H01L 29/0673 (2013.01); H01L 29/4232 (2013.01); H01L 29/775 (2013.01); H01L 29/7851 (2013.01); H10B 12/056 (2023.02);
Abstract

Embodiments disclosed herein include stacked forksheet transistor devices, and methods of fabricating stacked forksheet transistor devices. In an example, an integrated circuit structure includes a backbone. A first transistor device includes a first vertical stack of semiconductor channels adjacent to an edge of the backbone. A second transistor device includes a second vertical stack of semiconductor channels adjacent to the edge of the backbone. The second transistor device is stacked on the first transistor device.


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