The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 14, 2024
Filed:
Jul. 26, 2022
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Cheng-Hung Chen, Tainan, TW;
Yu-Nu Hsu, Tainan, TW;
Chun-Chen Liu, Kaohsiung, TW;
Heng-Chi Huang, Zhudong Township, TW;
Chien-Chen Li, Hsinchu, TW;
Shih-Yen Chen, Hsinchu, TW;
Cheng-Nan Hsieh, Chubei, TW;
Kuo-Chio Liu, Hsinchu, TW;
Chen-Shien Chen, Zhubei, TW;
Chin-Yu Ku, Hsinchu, TW;
Te-Hsun Pang, Tainan, TW;
Yuan-Feng Wu, Tainan, TW;
Sen-Chi Chiang, Tainan, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Abstract
Package structures and methods for manufacturing the same are provided. The package structure includes a first bump structure formed over a first substrate. The first bump structure includes a first pillar layer formed over the first substrate and a first barrier layer formed over the first pillar layer. In addition, the first barrier layer has a first protruding portion laterally extending outside a first edge of the first pillar layer. The package structure further includes a second bump structure bonded to the first bump structure through a solder joint. In addition, the second bump structure includes a second pillar layer formed over a second substrate and a second barrier layer formed over the second pillar layer. The first protruding portion of the first barrier layer is spaced apart from the solder joint.