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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10658234 B1

PDFFull Text
Date of Patent:
May. 19, 2020

Filed:

Jul. 29, 2016

Formation method of interconnection structure of semiconductor device

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Min-Hsiu Hung, Tainan, TW;

Sung-Li Wang, Zhubei, TW;

Pei-Wen Wu, Xinfeng Township, Hsinchu County, TW;

Yida Li, Hsinchu, TW;

Chih-Wei Chang, Jhudong Township, Hsinchu County, TW;

Huang-Yi Huang, Hsinchu, TW;

Cheng-Tung Lin, Jhudong Township, Hsinchu County, TW;

Jyh-Cherng Sheu, Hsinchu, TW;

Yee-Chia Yeo, Hsinchu, TW;

Chi-On Chui, Hsinchu, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;

Attorney:

Birch, Stewart, Kolasch & Birch, LLP

Primary Examiner:

Shouxiang Hu

Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/485 (2006.01); H01L 21/285 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76856 (2013.01); H01L 21/28518 (2013.01); H01L 21/76841 (2013.01); H01L 21/76843 (2013.01); H01L 21/76846 (2013.01); H01L 21/76855 (2013.01); H01L 21/76862 (2013.01); H01L 21/76877 (2013.01); H01L 21/76889 (2013.01); H01L 23/485 (2013.01); H01L 23/5226 (2013.01); H01L 23/53209 (2013.01); H01L 23/53223 (2013.01); H01L 23/53238 (2013.01); H01L 23/53252 (2013.01); H01L 23/53266 (2013.01);
Abstract

Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dielectric layer over a semiconductor substrate and forming an opening in the dielectric layer to expose a conductive element. The method also includes forming a conductive layer over the conductive element and modifying an upper portion of the conductive layer using a plasma operation to form a modified region. The method further includes forming a conductive plug over the modified region.

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