The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 04, 2018

Filed:

Aug. 28, 2014
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Chi-Cheng Hung, Miaoli County, TW;

Wei-Liang Lin, Hsinchu, TW;

Yung-Sung Yen, Taipei County, TW;

Chun-Kuang Chen, Hsinchu Hsien, TW;

Ru-Gun Liu, Hsinchu County, TW;

Tsai-Sheng Gau, Hsinchu, TW;

Tzung-Chi Fu, Miaoli County, TW;

Ming-Sen Tung, Hsin-Chu, TW;

Fu-Jye Liang, Hsinchu County, TW;

Li-Jui Chen, Hsinchu, TW;

Meng-Wei Chen, Taichung, TW;

Kuei-Shun Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G03F 7/20 (2006.01);
U.S. Cl.
CPC ...
G03F 7/70633 (2013.01); G03F 7/705 (2013.01); G03F 7/70258 (2013.01);
Abstract

The present disclosure provides a method. The method includes forming a resist layer on a patterned substrate; collecting first overlay data from the patterned substrate; determining an overlay compensation based on mapping of second overlay data from an integrated circuit (IC) pattern to the first overlay data from the patterned substrate; performing a compensation process to a lithography system according to the overlay compensation; and thereafter performing a lithography exposing process to the resist layer by the lithography system, thereby imaging the IC pattern to the resist layer.


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