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For the Inventor, By the Inventor

Taipei, Taiwan

Yu-Sheng Hsieh

This inventor holds 15 USPTO granted patents. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2018-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yu-Sheng Hsieh. Retrieved from https://idiyas.com/inventor/yu-sheng-hsieh

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 15

% Patents Active = 100.0

Average Co-Inventor Count = 5.9

ph-index = 2

Forward Citations = 18(Granted Patents)


Company Filing History:

goldMedal15 out of 42,872 
 
Taiwan Semiconductor Manufacturing Comp. Ltd.
 patents

Years Active: 2018-2025

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15 patents (USPTO):Explore Patents
1. 12266847 - Semiconductor packages and manufacturing methods thereof (2025-04-01),
2. 12205888 - Semiconductor packages and methods of forming the same (2025-01-21),
3. 12148735 - Memory device and manufacturing method thereof (2024-11-19),
4. 11929319 - Integrated fan-out packages and methods of forming the same (2024-03-12),
5. 11855333 - Semiconductor packages and manufacturing methods thereof (2023-12-26),
6. 11515618 - Semiconductor packages and manufacturing methods thereof (2022-11-29),
7. 11335666 - Memory device and manufacturing method thereof (2022-05-17),
8. 11127708 - Package structure and method of manufacturing the same (2021-09-21),
9. 11075159 - Integrated fan-out packages and methods of forming the same (2021-07-27),
10. 10978782 - Semiconductor packages and manufacturing methods thereof (2021-04-13),
11. 10879170 - Semiconductor package and manufacturing method thereof (2020-12-29),
12. 10636713 - Semiconductor packages and manufacturing methods thereof (2020-04-28),
13. 10504865 - Package structure and method of manufacturing the same (2019-12-10),
14. 10183858 - Semiconductor structure and method of manufacturing the same (2019-01-22),
15. 10157807 - Sensor packages and manufacturing mehtods thereof (2018-12-18),

Title: Innovations of Yu-Sheng Hsieh in Semiconductor Technology

Introduction

Yu-Sheng Hsieh is a prominent inventor based in New Taipei, Taiwan. He has made significant contributions to the field of semiconductor technology, holding a total of 15 patents. His work focuses on advanced semiconductor packages and manufacturing methods, which are crucial for the development of modern electronic devices.

Latest Patents

Among his latest patents, Yu-Sheng Hsieh has developed innovative semiconductor packages and manufacturing methods. One notable patent involves sensor packages that include a semiconductor chip and a redistribution layer structure. This design features an antenna transmitter structure positioned alongside the semiconductor chip and an antenna receiver structure located over the sensing surface of the semiconductor chip. Another significant patent details semiconductor packages that consist of two dies, an encapsulant, a first metal line, and a plurality of dummy vias. The encapsulant is strategically placed between the two dies, while the first metal line connects them electrically, enhancing the overall functionality of the semiconductor package.

Career Highlights

Yu-Sheng Hsieh is currently employed at Taiwan Semiconductor Manufacturing Company Limited, a leading firm in the semiconductor industry. His expertise and innovative approach have positioned him as a key player in the development of cutting-edge semiconductor technologies.

Collaborations

Throughout his career, Yu-Sheng Hsieh has collaborated with notable colleagues, including Yung-Ping Chiang and Han-Ping Pu. These collaborations have further enriched his work and contributed to the advancement of semiconductor technology.

Conclusion

In summary, Yu-Sheng Hsieh's contributions to semiconductor technology through his patents and collaborations highlight his role as an influential inventor in the field. His innovative designs continue to shape the future of electronic devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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