Yu-Ching Lee

This inventor holds 27 USPTO granted patents, primarily in Semiconductor Fabrication. Top assignees: Taiwan Semiconductor Manufacturing Comp. Ltd., Coretronic Corporation. Active years: 2018-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yu-Ching Lee. Retrieved from https://idiyas.com/inventor/yu-ching-lee

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 27

% Patents Active = 100.0

Average Co-Inventor Count = 2.9

ph-index = 2

Forward Citations = 14(Granted Patents)

Location History:

Hsin-Chu, TW (2018 - 2020)
Kaohsiung, TW (2018 - 2024)

Company Filing History:

26 out of 42,872

Taiwan Semiconductor Manufacturing Comp. Ltd.

patents

1 out of 1,255

Coretronic Corporation

patents

Years Active: 2018-2025

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Areas of Expertise:

Acoustic Measurement

Overlay Error Determination

Semiconductor Structure

Multi-Function Overlay Marks

Optical Reticle

Pellicle Assembly

Photomask Transportation

Film Thickness Measurement

Dummy Via

Lithography

Reticle Container

27 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 12320782 - Acoustic measurement of fabrication equipment clearance (2025-06-03),

2. 12189304 - Method and structures for acoustic wave overlay error determination (2025-01-07),

3. 12055860 - Multi-function overlay marks for reducing noise and extracting focus and critical dimension information (2024-08-06),

4. 11955441 - Interconnect structure and forming method thereof (2024-04-09),

5. 11837486 - Reticle transportation container (2023-12-05),

6. 11835864 - Multi-function overlay marks for reducing noise and extracting focus and critical dimension information (2023-12-05),

7. 11768443 - Method for manufacturing semiconductor structure (2023-09-26),

8. 11709153 - Acoustic measurement of fabrication equipment clearance (2023-07-25),

9. 11448975 - Multi-function overlay marks for reducing noise and extracting focus and critical dimension information (2022-09-20),

10. 11378892 - Overlay-shift measurement system (2022-07-05),

11. 11302654 - Method of fabricating semiconductor device including dummy via anchored to dummy metal layer (2022-04-12),

12. 11022889 - Overlay-shift measurement system and method for manufacturing semiconductor structure and measuring alignment mark of semiconductor structure (2021-06-01),

13. 11018037 - Optical reticle load port (2021-05-25),

14. 10998213 - Reticle transportation container (2021-05-04),

15. 10962888 - Structures for acoustic wave overlay error determination using periodic structures (2021-03-30),

Title: The Innovative Journey of Yu-Ching Lee

Introduction: Yu-Ching Lee, a pioneering inventor hailing from Kaohsiung, Taiwan, has made significant contributions to the field of technology with her groundbreaking inventions.

Latest Patents: Yu-Ching Lee holds several patents in the areas of renewable energy technologies, sustainable materials, and advanced electronics, showcasing her commitment to innovation and sustainability.

Career Highlights: With a career spanning over two decades, Yu-Ching Lee has worked tirelessly to develop cutting-edge solutions that address pressing global challenges. Her work has been recognized with numerous awards and accolades in the industry.

Collaborations: Throughout her career, Yu-Ching Lee has collaborated with leading research institutions, universities, and technology companies to further her inventions and bring them to market. Her collaborative spirit has led to the successful implementation of several groundbreaking technologies.

Conclusion: Yu-Ching Lee's passion for innovation, coupled with her dedication to creating a more sustainable future, has solidified her reputation as a trailblazing inventor in the field of technology. Her contributions continue to inspire the next generation of inventors and shape the landscape of technological advancements.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]