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For the Inventor, By the Inventor

San Jose, CA, United States of America

Victor W Lee

This inventor holds 52 USPTO granted patents and 12 published patent applications and 3 EPO patents, primarily in In-Memory Computation (CPC class G06F). Top assignees: Intel Corporation, Apple Inc., Rambus Inc.. Active years: 2003-2023.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Victor W Lee. Retrieved from https://idiyas.com/inventor/victor-w-lee

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 52 

% Patents Active = 46.2

 

Average Co-Inventor Count = 4.5

ph-index = 9

Forward Citations = 202(Granted Patents)

Forward Citations (Not Self Cited) = 193(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • Livingston, NJ (US) (2005)
  • San Jose, CA (US) (2005 - 2018)
  • Santa Clara, CA (US) (2003 - 2023)

Company Filing History:

goldMedal49 out of 56,365 
 
Intel Corporation
 patents
silverMedal1 out of 43,632 
 
Apple Inc.
 patents
bronzeMedal1 out of 2,959 
 
Rambus Inc.
 patents
4. 1 out of 834,570 
Other
 patents

Years Active: 2003-2023

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Areas of Expertise:
Adaptive Antenna Tuning
In-Memory Neural Cache
Power Management
Vector Instructions
SIMD Execution
Multicore Processors
Texture Units
High Performance Computing
Data Prefetching
Memory Hierarchy
Conditionally Evaluated Values
Loop Vectorization
52 patents (USPTO):Explore Patents
1. 11569858 - Adaptive antenna tuning system (2023-01-31),
2. 11502696 - In-memory analog neural cache (2022-11-15),
3. 11416165 - Low synch dedicated accelerator with in-memory computation capability (2022-08-16),
4. 11347994 - Weight prefetch for in-memory neural network execution (2022-05-31),
5. 11151046 - Programmable interface to in-memory cache processor (2021-10-19),
6. 10884957 - Pipeline circuit architecture to provide in-memory computation functionality (2021-01-05),
7. 10775873 - Performing power management in a multicore processor (2020-09-15),
8. 10768989 - Virtual vector processing (2020-09-08),
9. 10719317 - Hardware apparatuses and methods relating to elemental register accesses (2020-07-21),
10. 10705967 - Programmable interface to in-memory cache processor (2020-07-07),
11. 10656944 - Hardware apparatus and methods to prefetch a multidimensional block of elements from a multidimensional array (2020-05-19),
12. 10579378 - Instructions for manipulating a multi-bit predicate register for predicating instruction sequences (2020-03-03),
13. 10372450 - Systems, apparatuses, and methods for setting an output mask in a destination writemask register from a source write mask register using an input writemask and immediate (2019-08-06),
14. 10234930 - Performing power management in a multicore processor (2019-03-19),
15. 10152325 - Instruction and logic to provide pushing buffer copy and store functionality (2018-12-11),

Title: Inventor Victor W Lee - Revolutionizing Technology in San Jose, CA

Introduction: Victor W Lee is a visionary inventor based in San Jose, CA, known for his groundbreaking contributions to the field of technology.

Latest Patents: Victor W Lee holds several patents in the areas of artificial intelligence, machine learning, and robotics, showcasing his innovative approach to solving complex problems.

Career Highlights: With a career spanning over two decades, Victor W Lee has worked with leading tech companies, spearheading projects that have pushed the boundaries of technological advancements.

Collaborations: Throughout his career, Victor W Lee has collaborated with top researchers, engineers, and scientists, fostering a culture of innovation and creativity in the projects he undertakes.

Conclusion: Victor W Lee's passion for innovation and his relentless pursuit of excellence continue to inspire the next generation of inventors and technologists.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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