The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 19, 2019

Filed:

Feb. 13, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Victor W. Lee, Santa Clara, CA (US);

Edward T. Grochowski, San Jose, CA (US);

Daehyun Kim, San Jose, CA (US);

Yuxin Bai, San Jose, CA (US);

Sheng Li, Santa Clara, CA (US);

Naveen K. Mellempudi, Bangalore, IN;

Dhiraj D. Kalamkar, Bangalore, IN;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01); G06F 1/3287 (2019.01); G06F 1/324 (2019.01); G06F 1/3234 (2019.01); G06F 1/3225 (2019.01); G06F 1/329 (2019.01); G06F 1/3296 (2019.01); G06F 9/50 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3287 (2013.01); G06F 1/324 (2013.01); G06F 1/329 (2013.01); G06F 1/3225 (2013.01); G06F 1/3275 (2013.01); G06F 1/3296 (2013.01); G06F 9/50 (2013.01); Y02D 10/126 (2018.01); Y02D 10/14 (2018.01); Y02D 10/171 (2018.01); Y02D 10/172 (2018.01); Y02D 10/24 (2018.01);
Abstract

In an embodiment, a processor includes: a plurality of first cores to independently execute instructions, each of the plurality of first cores including a plurality of counters to store performance information; at least one second core to perform memory operations; and a power controller to receive performance information from at least some of the plurality of counters, determine a workload type executed on the processor based at least in part on the performance information, and based on the workload type dynamically migrate one or more threads from one or more of the plurality of first cores to the at least one second core for execution during a next operation interval. Other embodiments are described and claimed.


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