For the Inventor, By the Inventor

Enter assignee name

San Jose, CA, United States of America

Rambus Inc.

Calculating rank

USPTO Granted Patents = 2,959

% Expired Patents = 24.0

CIPO Patents = 1

EPO Patents = 174

Trademarks = 7

Forward Citations = 42,308

Loading Chart...

Loading Chart...

581 inventors (with patents filed for the assignee):

Frederick Abbott Ware (763 out of 800 patents)

Craig Edward Hampel (298 out of 312 patents)

Jared L Zerbe (239 out of 258 patents)

4. Ely K Tsern (233 out of 249 patents)

5. Ian P Shaeffer (219 out of 235 patents)

6. Mark A Horowitz (213 out of 246 patents)

7. Scott C Best (181 out of 207 patents)

8. John Eric Linstadt (172 out of 173 patents)

9. Thomas Vogelsang (146 out of 175 patents)

10. Brian S Leibowitz (139 out of 160 patents)

11. Richard E Perego (139 out of 145 patents)

12. Richard Maurice Barth (120 out of 125 patents)

13. Donald C Stark (105 out of 124 patents)

14. Kevin S Donnelly (104 out of 107 patents)

15. Steven Cameron Woo (103 out of 107 patents)

Core Competencies:

Dynamic Random Access Memory

Hybrid Memory

Low Latency Architecture

Error Detection

Memory Module

Data Storage

Interconnect Mapping

Memory System Design

High-Performance Memory

Cache Mode

Memory Buffer

Reliability Techniques

2,959 patents: Sort by Forward Citations

1. 12770675 - Memories and memory components with interconnected and redundant data interfaces (2026-10-20),

2. 12770673 - Active interposer system (2026-10-20),

3. 12769643 - DRAM metadata access (2026-10-20),

4. 12769486 - Stacked device communication (2026-10-20),

5. 12769356 - Memory system using asymmetric source-synchronous clocking (2026-10-20),

6. 12763130 - High capacity memory system using standard controller component (2026-10-13),

7. 12762069 - Training and operations with a double buffered memory topology (2026-10-13),

8. 12755772 - Methods and circuits for power management of a memory module (2026-10-06),

9. 12755771 - Mitigation of refresh management row hammer (2026-10-06),

10. 12754694 - Quad-data-rate (QDR) host interface in a memory system (2026-10-06),

11. 12739118 - Memory management with implicit identification of cryptographic keys using error correction data (2026-09-15),

12. 12737139 - Interface circuit for converting a serial data stream to a parallel data scheme with data strobe preamble information in the serial data stream (2026-09-15),

13. 12732358 - Secure key exchange in a multi-processor device (2026-09-08),

14. 12731632 - Sense amplifier for active standby operation (2026-09-08),

15. 12730587 - Joint command dynamic random access memory (DRAM) apparatus and methods (2026-09-08),

Company Overview

Rambus Inc., headquartered in San Jose, California, specializes in advanced memory and data storage technologies. The company focuses on dynamic random access memory (DRAM) and hybrid memory solutions, emphasizing low latency architecture and error detection to enhance performance and reliability in memory systems. Rambus is dedicated to innovating memory module design and interconnect mapping, positioning itself as a key player in the evolving landscape of data storage and memory system design.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 27 2026

2,959 Patents

#8 in San Jose, CA

#40 in California

#157 in US

#317 in the World

San Jose, CA, United States of America

Rambus Inc.

Forward Citations = 42,308

581 inventors:

Frederick Abbott Ware (763 out of 800 patents)

Craig Edward Hampel (298 out of 312 patents)

Jared L Zerbe (239 out of 258 patents)

4. Ely K Tsern (233 out of 249 patents)

5. Ian P Shaeffer (219 out of 235 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Rambus Inc.. Retrieved from https://idiyas.com/company/rambus

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

Loading…