For the Inventor, By the Inventor

Enter assignee name

San Jose, CA, United States of America

Rambus Inc.

USPTO Granted Patents = 2,952

% Expired Patents = 24.1

CIPO Patents = 1

EPO Patents = 173

Trademarks = 7

Forward Citations = 42,176

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581 inventors (with patents filed for the assignee):

Frederick Abbott Ware (760 out of 797 patents)

Craig Edward Hampel (298 out of 312 patents)

Jared L Zerbe (239 out of 258 patents)

4. Ely K Tsern (232 out of 248 patents)

5. Ian P Shaeffer (219 out of 235 patents)

6. Mark A Horowitz (213 out of 246 patents)

7. Scott C Best (179 out of 205 patents)

8. John Eric Linstadt (170 out of 171 patents)

9. Thomas Vogelsang (144 out of 173 patents)

10. Brian S Leibowitz (139 out of 160 patents)

11. Richard E Perego (139 out of 145 patents)

12. Richard Maurice Barth (120 out of 125 patents)

13. Donald C Stark (105 out of 124 patents)

14. Kevin S Donnelly (104 out of 107 patents)

15. Steven Cameron Woo (102 out of 106 patents)

Core Competencies:

Dynamic Random Access Memory

Hybrid Memory

Low Latency Architecture

Error Detection

Memory Module

Data Storage

Interconnect Mapping

Memory System Design

High-Performance Memory

Cache Mode

Memory Buffer

Reliability Techniques

2,952 patents: Sort by Forward Citations

1. 12755772 - Methods and circuits for power management of a memory module (2026-10-06),

2. 12755771 - Mitigation of refresh management row hammer (2026-10-06),

3. 12754694 - Quad-data-rate (QDR) host interface in a memory system (2026-10-06),

4. 12739118 - Memory management with implicit identification of cryptographic keys using error correction data (2026-09-15),

5. 12737139 - Interface circuit for converting a serial data stream to a parallel data scheme with data strobe preamble information in the serial data stream (2026-09-15),

6. 12732358 - Secure key exchange in a multi-processor device (2026-09-08),

7. 12731632 - Sense amplifier for active standby operation (2026-09-08),

8. 12730587 - Joint command dynamic random access memory (DRAM) apparatus and methods (2026-09-08),

9. 12724729 - Local internal discovery and configuration of individually selected and jointly selected devices (2026-09-01),

10. 12724728 - Protocol including timing calibration between memory request and data transfer (2026-09-01),

11. 12720909 - Synchronous wired-or ack status for memory with variable write latency (2026-08-25),

12. 12719454 - Methods and circuits for slew-rate calibration (2026-08-25),

13. 12717488 - Device assisted cold page tracking (2026-08-25),

14. 12712000 - MEMORY BANDWIDTH AGGREGATION USING SIMULTANEOUS ACCESS OF STACKED SEMICONDUCTOR MEMORY DIE (2026-08-18),

15. 12710875 - HOT DATA DETECTION FOR DISAGGREGATED MEMORY USING BLOOM FILTERS (2026-08-18),

Company Overview

Rambus Inc., headquartered in San Jose, California, specializes in advanced memory and data storage technologies. The company focuses on dynamic random access memory (DRAM) and hybrid memory solutions, emphasizing low latency architecture and error detection to enhance performance and reliability in memory systems. Rambus is dedicated to innovating memory module design and interconnect mapping, positioning itself as a key player in the evolving landscape of data storage and memory system design.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 6 2026

2,952 Patents

#8 in San Jose, CA

#40 in California

#157 in US

#318 in the World

San Jose, CA, United States of America

Rambus Inc.

Forward Citations = 42,176

581 inventors:

Frederick Abbott Ware (760 out of 797 patents)

Craig Edward Hampel (298 out of 312 patents)

Jared L Zerbe (239 out of 258 patents)

4. Ely K Tsern (232 out of 248 patents)

5. Ian P Shaeffer (219 out of 235 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Rambus Inc.. Retrieved from https://idiyas.com/company/rambus

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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