The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 31, 2022
Filed:
Oct. 15, 2018
Intel Corporation, Santa Clara, CA (US);
Amrita Mathuriya, Portland, OR (US);
Sasikanth Manipatruni, Portland, OR (US);
Victor Lee, Santa Clara, CA (US);
Huseyin Sumbul, Portland, OR (US);
Gregory Chen, Portland, CA (US);
Raghavan Kumar, Hillsboro, OR (US);
Phil Knag, Hillsboro, OR (US);
Ram Krishnamurthy, Portland, OR (US);
Ian Young, Portland, OR (US);
Abhishek Sharma, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
The present disclosure is directed to systems and methods of bit-serial, in-memory, execution of at least an nlayer of a multi-layer neural network in a first on-chip processor memory circuitry portion contemporaneous with prefetching and storing layer weights associated with the (n+1)layer of the multi-layer neural network in a second on-chip processor memory circuitry portion. The storage of layer weights in on-chip processor memory circuitry beneficially decreases the time required to transfer the layer weights upon execution of the (n+1)layer of the multi-layer neural network by the first on-chip processor memory circuitry portion. In addition, the on-chip processor memory circuitry may include a third on-chip processor memory circuitry portion used to store intermediate and/or final input/output values associated with one or more layers included in the multi-layer neural network.