Intel Corporation

Other

Apple Inc.

Rambus Inc.

Tahoe Research, Ltd.

Victor W Lee

Daehyun Kim

Changkyu Kim

Christopher J Hughes

Yen-Kuang Chen

Mikhail Smelyanskiy

Sara S Baghsorkhi

Jayashankar Bharadwaj

Albert Hartono

Nalini Vasudevan

Jatin Chhugani

Sasikanth Manipatruni

Amrita Mathuriya

Ian A Young

Abhishek A Sharma

Ram K Krishnamurthy

Raghavan Kumar

Gregory Kengho Chen

Phil Knag

Huseyin Ekin Sumbul

Nadathur Rajagopalan Satish

Naveen K Mellempudi

Anthony-Trung D Nguyen

Sheng C Li

Phanindra Mannava

Anthony Nguyen

Yuxin Bai

Edward Thomas Grochowski

Sanjeev Kumar

Aaron T Spink

Ganesh Suryanarayan Dasika

Tin-Fook Ngai

Jose Gonzalez

Dhiraj D Kalamkar

Julio Gago

Santiago Galan

Victor Moya Del Barrio

Robert Valentine

Mark Jay Charney

Alexander F Heinecke

Milind Baburao Girkar

Jong Soo Park

Akhilesh Kumar

George Zacharias Chrysos

Ugonna C Echeruo

Mattia Pascolini

Rajesh M Sankaran

Cheng C Wang

Youfeng Wu

Matthew A Mow

Sanjay Dabral

Tatiana Shpeisman

Enrique Ayala Vazquez

Sanjay Kumar

Ioannis T Schoinas

Lawrence Lai

Hongfei Hu

Nanbo Jin

Ming-Ju Tsai

James A Gasbarro

Liang Han

Erdinc Irci

Yijun Zhou

Thomas E Biedka

Michael J Espig

Yiren Wang

Paul M Petersen

Arch D Robison

Doddaballapur N Jayasimha

Tak Ming Mak

James G Judkins

Subramanya R Dulloor

Hongbo Rong

Boris A Babayan

Todd A Anderson

Henry Stracovsky

Yuancheng Xu

Peng Tu

William Macy

Sergey A Rozhkov

Shihao Ji

Engin Ipek

Hai Liu

P G Lowney

Kim Daehyun

K Phanindra Mannava

Sheng Li

A radio frequency device has a multifunctional tuner that stores measurements of reflection coefficient parameter in a register. The radio frequency device also has a transceiver that has a transmitter. The transceiver may detect a transmitter signal from the transmitter to an antenna in an initial tuning state and then determine whether the transmitter signal is stable. In response to the transmitter signal being stable, the transceiver may measuring the reflection coefficient parameters at the multifunctional tuner. Furthermore, the radio frequency device has a baseband controller that has a memory to store instructions and a processor to execute the instructions. The instructions cause the processor to determine an antenna impedance based on the reflection coefficient parameters, and in response to determining that the antenna impedance is greater than or less than a threshold antenna impedance, iteratively tune the antenna using the multifunctional tuner.

Adaptive antenna tuning system

Embodiments are directed to systems and methods of implementing an analog neural network using a pipelined SRAM architecture ('PISA') circuitry disposed in on-chip processor memory circuitry. The on-chip processor memory circuitry may include processor last level cache (LLC) circuitry. One or more physical parameters, such as a stored charge or voltage, may be used to permit the generation of an in-memory analog output using a SRAM array. The generation of an in-memory analog output using only word-line and bit-line capabilities beneficially increases the computational density of the PISA circuit without increasing power requirements. Thus, the systems and methods described herein beneficially leverage the existing capabilities of on-chip SRAM processor memory circuitry to perform a relatively large number of analog vector/tensor calculations associated with execution of a neural network, such as a recurrent neural network, without burdening the processor circuitry and without significant impact to the processor power requirements.

In-memory analog neural cache

The present disclosure is directed to systems and methods of implementing a neural network using in-memory, bit-serial, mathematical operations performed by a pipelined SRAM architecture (bit-serial PISA) circuitry disposed in on-chip processor memory circuitry. The on-chip processor memory circuitry may include processor last level cache (LLC) circuitry. The bit-serial PISA circuitry is coupled to PISA memory circuitry via a relatively high-bandwidth connection to beneficially facilitate the storage and retrieval of layer weights by the bit-serial PISA circuitry during execution. Direct memory access (DMA) circuitry transfers the neural network model and input data from system memory to the bit-serial PISA memory and also transfers output data from the PISA memory circuitry to system memory circuitry. Thus, the systems and methods described herein beneficially leverage the on-chip processor memory circuitry to perform a relatively large number of vector/tensor calculations without burdening the processor circuitry.

Low synch dedicated accelerator with in-memory computation capability

The present disclosure is directed to systems and methods of bit-serial, in-memory, execution of at least an nlayer of a multi-layer neural network in a first on-chip processor memory circuitry portion contemporaneous with prefetching and storing layer weights associated with the (n+1)layer of the multi-layer neural network in a second on-chip processor memory circuitry portion. The storage of layer weights in on-chip processor memory circuitry beneficially decreases the time required to transfer the layer weights upon execution of the (n+1)layer of the multi-layer neural network by the first on-chip processor memory circuitry portion. In addition, the on-chip processor memory circuitry may include a third on-chip processor memory circuitry portion used to store intermediate and/or final input/output values associated with one or more layers included in the multi-layer neural network.

Weight prefetch for in-memory neural network execution

The present disclosure is directed to systems and methods of implementing a neural network using in-memory mathematical operations performed by pipelined SRAM architecture (PISA) circuitry disposed in on-chip processor memory circuitry. A high-level compiler may be provided to compile data representative of a multi-layer neural network model and one or more neural network data inputs from a first high-level programming language to an intermediate domain-specific language (DSL). A low-level compiler may be provided to compile the representative data from the intermediate DSL to multiple instruction sets in accordance with an instruction set architecture (ISA), such that each of the multiple instruction sets corresponds to a single respective layer of the multi-layer neural network model. Each of the multiple instruction sets may be assigned to a respective SRAM array of the PISA circuitry for in-memory execution. Thus, the systems and methods described herein beneficially leverage the on-chip processor memory circuitry to perform a relatively large number of in-memory vector/tensor calculations in furtherance of neural network processing without burdening the processor circuitry.

Programmable interface to in-memory cache processor

Techniques and mechanisms for performing in-memory computations with circuitry having a pipeline architecture. In an embodiment, various stages of a pipeline each include a respective input interface and a respective output interface, distinct from said input interface, to couple to different respective circuitry. These stages each further include a respective array of memory cells and circuitry to perform operations based on data stored by said array. A result of one such in-memory computation may be communicated from one pipeline stage to a respective next pipeline stage for use in further in-memory computations. Control circuitry, interconnect circuitry, configuration circuitry or other logic of the pipeline precludes operation of the pipeline as a monolithic, general-purpose memory device. In other embodiments, stages of the pipeline each provide a different respective layer of a neural network.

Pipeline circuit architecture to provide in-memory computation functionality

In an embodiment, a processor includes: a plurality of first cores to independently execute instructions, each of the plurality of first cores including a plurality of counters to store performance information; at least one second core to perform memory operations; and a power controller to receive performance information from at least some of the plurality of counters, determine a workload type executed on the processor based at least in part on the performance information, and based on the workload type dynamically migrate one or more threads from one or more of the plurality of first cores to the at least one second core for execution during a next operation interval. Other embodiments are described and claimed.

Performing power management in a multicore processor

Methods and apparatus to provide virtualized vector processing are described. In one embodiment, one or more operations corresponding to a virtual vector request are distributed to one or more processor cores for execution.

Virtual vector processing

Methods and apparatuses relating to a vector instruction with a register operand with an elemental offset are described. In one embodiment, a hardware processor includes a decode unit to decode a vector instruction with a register operand with an elemental offset to access a first number of elements in a register specified by the register operand, wherein the first number is a total number of elements in the register minus the elemental offset, access a second number of elements in a next logical register, wherein the second number is the elemental offset, and combine the first number of elements and the second number of elements as a data vector, and an execution unit to execute the vector instruction on the data vector.

Hardware apparatuses and methods relating to elemental register accesses

Methods and apparatuses relating to a prefetch instruction to prefetch a multidimensional block of elements from a multidimensional array into a cache. In one embodiment, a hardware processor includes a decoder to decode a prefetch instruction to prefetch a multidimensional block of elements from a multidimensional array into a cache, wherein at least one operand of the prefetch instruction is to indicate a system memory address of an element of the multidimensional block of elements, a stride of the multidimensional block of elements, and boundaries of the multidimensional block of elements, and an execution unit to execute the prefetch instruction to generate system memory addresses of the other elements of the multidimensional block of elements, and load the multidimensional block of elements into the cache from the system memory addresses.

Hardware apparatus and methods to prefetch a multidimensional block of elements from a multidimensional array

An apparatus and method are described for executing instructions using a predicate register. For example, one embodiment of a processor comprises: a register set including a predicate register to store a set of predicate condition bits, the predicate condition bits specifying whether results of a particular predicated instruction sequence are to be retained or discarded; and predicate execution logic to execute a first predicate instruction to indicate a start of a new predicated instruction sequence by copying a condition value from a processor control register in the register set to the predicate register. In a further embodiment, the predicate condition bits in the predicate register are to be shifted in response to the first predicate instruction to free space within the predicate register for the new condition value associated with the new predicated instruction sequence.

Instructions for manipulating a multi-bit predicate register for predicating instruction sequences

Embodiments of systems, apparatuses, and methods for performing in a computer processor generation of a predicate mask based on vector comparison in response to a single instruction are described.

Systems, apparatuses, and methods for setting an output mask in a destination writemask register from a source write mask register using an input writemask and immediate

Instructions and logic provide pushing buffer copy and store functionality. Some embodiments include a first hardware thread or processing core, and a second hardware thread or processing core, a cache to store cache coherent data in a cache line for a shared memory address accessible by the second hardware thread or processing core. Responsive to decoding an instruction specifying a source data operand, said shared memory address as a destination operand, and one or more owner of said shared memory address, one or more execution units copy data from the source data operand to the cache coherent data in the cache line for said shared memory address accessible by said second hardware thread or processing core in the cache when said one or more owner includes said second hardware thread or processing core.

Instruction and logic to provide pushing buffer copy and store functionality

Growing community of inventors

San Jose, CA, United States of America

Victor W Lee