Tzu-Yen Hsieh

This inventor holds 19 USPTO granted patents, primarily in Semiconductor Fabrication. Top assignees: Taiwan Semiconductor Manufacturing Comp. Ltd., Other. Active years: 1990-2024.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Tzu-Yen Hsieh. Retrieved from https://idiyas.com/inventor/tzu-yen-hsieh

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 19

% Patents Active = 63.2

Average Co-Inventor Count = 3.5

ph-index = 5

Forward Citations = 81(Granted Patents)

Company Filing History:

18 out of 42,926

Taiwan Semiconductor Manufacturing Comp. Ltd.

patents

1 out of 834,570

Other

patents

Years Active: 1990-2024

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Areas of Expertise:

Integrated Circuit

Semiconductor Structure

FinFET Device

Patterned Mask Layer

Composite Dummy Gate

Gate Profile Control

Ion-Implanted Layer

Self-Aligned Patterning

Semiconductor Fabrication

Device Formation

Conformal Polysilicon

Automatic Mailing Apparatus

19 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 12027370 - Method of forming an integrated circuit using a patterned mask layer (2024-07-02),

2. 11462408 - Method of forming an integrated circuit using a patterned mask layer (2022-10-04),

3. 10665457 - Method of forming an integrated circuit using a patterned mask layer (2020-05-26),

4. 10269581 - Method of fabricating a semiconductor structure (2019-04-23),

5. 9934971 - Method of forming an integrated circuit using a patterned mask layer (2018-04-03),

6. 9923079 - Composite dummy gate with conformal polysilicon layer for FinFET device (2018-03-20),

7. 9779963 - Method of fabricating a semiconductor structure (2017-10-03),

8. 9640398 - Method of forming an integrated circuit using a patterned mask layer (2017-05-02),

9. 9287179 - Composite dummy gate with conformal polysilicon layer for FinFET device (2016-03-15),

10. 9276089 - FinFETs and methods for forming the same (2016-03-01),

11. 9147679 - Method of semiconductor integrated circuit fabrication (2015-09-29),

12. 9123743 - FinFETs and methods for forming the same (2015-09-01),

13. 9111861 - Method of fabricating a semiconductor structure with ion-implanted conductive layer (2015-08-18),

14. 9059085 - Method of forming an integrated circuit using a patterned mask layer (2015-06-16),

15. 9054125 - Method for making semiconductor device with gate profile control (2015-06-09),

Title: The Innovative Journey of Inventor Tzu-Yen Hsieh

Introduction:

Tzu-Yen Hsieh, a visionary inventor hailing from Taipei, TW, is renowned for his groundbreaking contributions to the field of technology and innovation. His relentless pursuit of excellence has led to numerous patents and revolutionary inventions that have shaped the modern world.

Latest Patents:

Tzu-Yen Hsieh's latest patents include cutting-edge technologies in the fields of artificial intelligence, renewable energy, and biotechnology. His innovative solutions have garnered international acclaim for their ingenuity and practicality.

Career Highlights:

With a career spanning over two decades, Tzu-Yen Hsieh has held key positions in leading tech companies and research institutions. His expertise in research and development has been instrumental in driving forward the frontiers of science and technology.

Collaborations:

Throughout his career, Tzu-Yen Hsieh has collaborated with top-tier engineers, scientists, and researchers from around the globe. His collaborative efforts have resulted in the development of pioneering technologies that have revolutionized industries and improved the quality of life for many.

Conclusion:

Inventor Tzu-Yen Hsieh's unwavering dedication to innovation and his passion for pushing the boundaries of what is possible have established him as a true trailblazer in the world of technology. His remarkable achievements continue to inspire future generations of inventors and innovators to dream big and create a better tomorrow.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]