The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 20, 2018
Filed:
Mar. 02, 2016
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Inventors:
Yuan-Sheng Huang, Taichung, TW;
Chao-Cheng Chen, Hsin-Chu, TW;
Ryan Chia-Jen Chen, Taiwan, SG;
Ming-Ching Chang, Hsinchu, TW;
Tzu-Yen Hsieh, Taipei, TW;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 21/823807 (2013.01); H01L 21/823821 (2013.01); H01L 21/823828 (2013.01); H01L 27/0924 (2013.01); H01L 29/0649 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract
A method includes providing a fin structure containing a semiconductor material. The method includes forming a gate dielectric layer over the fin structure, the gate dielectric layer being at least partially wrapped around the fin structure. The method includes forming a gate layer over the gate dielectric layer, wherein the gate layer is formed in a conformal manner. The method includes forming a dummy gate layer over the gate layer.